Browsing by Author Cheng, Chao Ching

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Showing results 1 to 13 of 13
TitleAuthor(s)Issue Date
 
Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics
Proceeding/Conference:Technical Digest - International Electron Devices Meeting, IEDM
Chou, Ang ShengWu, TongCheng, Chao ChingZhan, Shun SiangNi, I. ChihWang, Shih YunChang, Yu ChenLiew, San LinChen, EdwardChang, Wen HaoWu, Chih I.Cai, JinWong, H. S.PhilipWang, Han
2021
 
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS<inf>2</inf> Channel Directly Grown on SiO<inf>x</inf>/Si Substrates Using Area-Selective CVD Technology
Journal:IEEE Transactions on Electron Devices
Chung, Yun YanShieh, Jia MinSu, Sheng KaiChiang, Hung LiChen, Tzu ChiangLi, Lain JongWong, H. S.PhilipJian, Wen BinChien, Chao HsinLu, Kuan ChengCheng, Chao ChingLi, Ming YangLin, Chao TingLi, Chi FengChen, Jyun HongLai, Tung YenLi, Kai Shin
2019
 
Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS<inf>2</inf>FETs for SoC Scaling
Journal:IEEE Transactions on Electron Devices
Hu, Vita Pi HoSu, Cheng WeiLee, Yen WeiHo, Tun YiCheng, Chao ChingChen, Tzu ChiangHung, Terry Yi TseLi, Jin FuChen, Yu GuangLi, Lain Jong
2020
 
First demonstration of 40-nm channel length top-gate WS<inf>2</inf> pFET using channel area-selective CVD growth directly on SiO<inf>x</inf>/Si substrate
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Cheng, Chao ChingChung, Yun YanLi, Uing YangLin, Chao TingLi, Chi FengChen, Jyun HongLai, Tung YenLi, Kai ShinShieh, Jia MinSu, Sheng KaiChiang, Hung LiChen, Tzu ChiangLi, Lain JongWong, H. S.PhilipChien, Chao Hsin
2019
 
First Demonstration of GAA Monolayer-MoS<inf>2</inf>Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length
Proceeding/Conference:Technical Digest - International Electron Devices Meeting, IEDM
Chung, Yun YanChou, Bo JhihHsu, Chen FengYun, Wei ShengLi, Ming YangSu, Sheng KaiLiao, Yu TsungLee, Meng ChienHuang, Guo WeiLiew, San LinShen, Yun YangChang, Wen HaoChen, Chien WeiKei, Chi ChungWang, HanPhilip Wong, H. S.Lee, T. Y.Chien, Chao HsinCheng, Chao ChingRadu, Iuliana P.
2022
 
High On-Current 2D nFET of 390 \mu A/\mu m at V_{DS = 1V using Monolayer CVD MoS2 without Intentional Doping
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Chou, Ang ShengShen, Pin ChunCheng, Chao ChingLu, Li SyuanChueh, Wei ChenLi, Ming YangPitner, GregoryChang, Wen HaoWu, Chih I.Kong, JingLi, Lain JongWong, H. S.Philip
2020
 
High On-State Current in Chemical Vapor Deposited Monolayer MoS<inf>2</inf>nFETs with Sn Ohmic Contacts
Journal:IEEE Electron Device Letters
Chou, Ang ShengCheng, Chao ChingLiew, San LinHo, Po HsunWang, Shih YunChang, Yu ChenChang, Che KangSu, Yuan ChunHuang, Zheng DaFu, Fang YuHsu, Chen FengChung, Yun YanChang, Wen HaoLi, Lain JongWu, Chih I.
2021
 
High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory
Journal:IEEE Electron Device Letters
Chung, Yun YanCheng, Chao ChingChou, Yu CheChueh, Wei ChenChung, Wan HsuanYu, ZhihaoHung, Terry Yi TseHuang, Lin YunWang, Shin YuanTeng, Li ChengChang, Wen HoLi, Lain JongChien, Chao Hsin
2020
 
Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator Circuits
Proceeding/Conference:Technical Digest - International Electron Devices Meeting, IEDM
Cheng, Chao ChingLi, Lain JongWong, H. S.PhilipLu, Chun ChiehChao, Tsu AngChou, Ang ShengChiang, Hung LiChen, Tzu ChiangGao, TianqiZhao, JianwenCui, Zheng
2019
 
Nearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm
Proceeding/Conference:Technical Digest - International Electron Devices Meeting, IEDM
Lee, Tsung EnSu, Yuan ChunLin, Bo JiunChen, Yi XuanYun, Wei ShengHo, Po HsunWang, Jer FuSu, Sheng KaiHsu, Chen FengMao, Po SenChang, Yu ChengChien, Chao HsinLiu, Bo HengSu, Chien YingKei, Chi ChungWang, HanPhilip Wong, H. S.Lee, T. Y.Chang, Wen HaoCheng, Chao ChingRadu, Iuliana P.
2022
 
Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Su, Sheng KaiChen, EdwardHung, Terry Y.T.Li, Meng ZhanPitner, GregoryCheng, Chao ChingWang, HanCai, JinWong, H. S.PhilipRadu, Iuliana P.
2022
 
Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS<inf>2</inf>
Journal:ACS Nano
Sun, ZhengPang, Chin ShengWu, PengHung, Terry Y.T.Li, Ming YangLiew, San LinCheng, Chao ChingWang, HanWong, H. S.PhilipLi, Lain JongRadu, IulianaChen, ZhihongAppenzeller, Joerg
2022
 
Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS<inf>2</inf>Transistor
Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology
Li, Ming YangHsu, Ching HaoShen, Shin WeiChou, Ang ShengLin, Yuxuan CosmiChuu, Chih PiaoYang, NingChou, Sui AnHuang, Lin YunCheng, Chao ChingWoon, Wei YenLiao, SzuyaWu, Chih I.Li, Lain JongRadu, IulianaWong, H. S.PhilipWang, Han
2022
Showing results 1 to 13 of 13