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Conference Paper: Nearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm

TitleNearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm
Authors
Issue Date2022
Citation
Technical Digest - International Electron Devices Meeting, IEDM, 2022, v. 2022-December, p. 741-744 How to Cite?
AbstractTransistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS2 to build top-gate nFET with EOT 1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high varepsilon-{ mathrm{e} mathrm{f} mathrm{f}} 13.53, a large mathrm{E}-{ mathrm{B} mathrm{D}} 12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.
Persistent Identifierhttp://hdl.handle.net/10722/335438
ISSN
2020 SCImago Journal Rankings: 0.827

 

DC FieldValueLanguage
dc.contributor.authorLee, Tsung En-
dc.contributor.authorSu, Yuan Chun-
dc.contributor.authorLin, Bo Jiun-
dc.contributor.authorChen, Yi Xuan-
dc.contributor.authorYun, Wei Sheng-
dc.contributor.authorHo, Po Hsun-
dc.contributor.authorWang, Jer Fu-
dc.contributor.authorSu, Sheng Kai-
dc.contributor.authorHsu, Chen Feng-
dc.contributor.authorMao, Po Sen-
dc.contributor.authorChang, Yu Cheng-
dc.contributor.authorChien, Chao Hsin-
dc.contributor.authorLiu, Bo Heng-
dc.contributor.authorSu, Chien Ying-
dc.contributor.authorKei, Chi Chung-
dc.contributor.authorWang, Han-
dc.contributor.authorPhilip Wong, H. S.-
dc.contributor.authorLee, T. Y.-
dc.contributor.authorChang, Wen Hao-
dc.contributor.authorCheng, Chao Ching-
dc.contributor.authorRadu, Iuliana P.-
dc.date.accessioned2023-11-17T08:25:54Z-
dc.date.available2023-11-17T08:25:54Z-
dc.date.issued2022-
dc.identifier.citationTechnical Digest - International Electron Devices Meeting, IEDM, 2022, v. 2022-December, p. 741-744-
dc.identifier.issn0163-1918-
dc.identifier.urihttp://hdl.handle.net/10722/335438-
dc.description.abstractTransistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS2 to build top-gate nFET with EOT 1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high varepsilon-{ mathrm{e} mathrm{f} mathrm{f}} 13.53, a large mathrm{E}-{ mathrm{B} mathrm{D}} 12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.-
dc.languageeng-
dc.relation.ispartofTechnical Digest - International Electron Devices Meeting, IEDM-
dc.titleNearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/IEDM45625.2022.10019552-
dc.identifier.scopuseid_2-s2.0-85147529004-
dc.identifier.volume2022-December-
dc.identifier.spage741-
dc.identifier.epage744-

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