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Conference Paper: First Demonstration of GAA Monolayer-MoS2Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

TitleFirst Demonstration of GAA Monolayer-MoS<inf>2</inf>Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length
Authors
Issue Date2022
Citation
Technical Digest - International Electron Devices Meeting, IEDM, 2022, v. 2022-December, p. 3451-3454 How to Cite?
AbstractThis work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.
Persistent Identifierhttp://hdl.handle.net/10722/335435
ISSN
2020 SCImago Journal Rankings: 0.827

 

DC FieldValueLanguage
dc.contributor.authorChung, Yun Yan-
dc.contributor.authorChou, Bo Jhih-
dc.contributor.authorHsu, Chen Feng-
dc.contributor.authorYun, Wei Sheng-
dc.contributor.authorLi, Ming Yang-
dc.contributor.authorSu, Sheng Kai-
dc.contributor.authorLiao, Yu Tsung-
dc.contributor.authorLee, Meng Chien-
dc.contributor.authorHuang, Guo Wei-
dc.contributor.authorLiew, San Lin-
dc.contributor.authorShen, Yun Yang-
dc.contributor.authorChang, Wen Hao-
dc.contributor.authorChen, Chien Wei-
dc.contributor.authorKei, Chi Chung-
dc.contributor.authorWang, Han-
dc.contributor.authorPhilip Wong, H. S.-
dc.contributor.authorLee, T. Y.-
dc.contributor.authorChien, Chao Hsin-
dc.contributor.authorCheng, Chao Ching-
dc.contributor.authorRadu, Iuliana P.-
dc.date.accessioned2023-11-17T08:25:52Z-
dc.date.available2023-11-17T08:25:52Z-
dc.date.issued2022-
dc.identifier.citationTechnical Digest - International Electron Devices Meeting, IEDM, 2022, v. 2022-December, p. 3451-3454-
dc.identifier.issn0163-1918-
dc.identifier.urihttp://hdl.handle.net/10722/335435-
dc.description.abstractThis work demonstrates the first successful integration of monolayer MoS2 nanosheet FET in a gate-all-around configuration. At a gate length of 40nm, the transistor exhibits a remarkable mathrm{I}-{ mathrm{ON}} sim 410 mu mathrm{A}/ { mu} mathrm{m} at mathrm{V}-{ mathrm{DS}}=1 mathrm{V}, achieved with a monolayer channel, '0.7 nm thin. The FET has a large mathrm{I}-{ mathrm{ON}}/ mathrm{I}-{ mathrm{OFF}} gt 1 mathrm{E}8, positive mathrm{V}-{ mathrm{TH}} sim 1.4 mathrm{V} with nearly zero DIBL. Higher drive current can be achieved through stacking of multiple channel layers. We propose here a fully integrated flow and we detail the feasibility of the most critical modules: stack/channel preparation, fin patterning, inner spacer, channel release, contact. The successful demonstration of MoS2 NS with high performance and of the stacked NS modules further clarifies the value proposition in 2D materials for transistor scaling.-
dc.languageeng-
dc.relation.ispartofTechnical Digest - International Electron Devices Meeting, IEDM-
dc.titleFirst Demonstration of GAA Monolayer-MoS<inf>2</inf>Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/IEDM45625.2022.10019563-
dc.identifier.scopuseid_2-s2.0-85147516196-
dc.identifier.volume2022-December-
dc.identifier.spage3451-
dc.identifier.epage3454-

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