First demonstration of 40-nm channel length top-gate WS<inf>2</inf> pFET using channel area-selective CVD growth directly on SiO<inf>x</inf>/Si substrate

Abstract

Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of 106, a S.S. of 97 mV/dec., and nearly zero DIBL. 2 2 2