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Article: High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory

TitleHigh-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory
Authors
Keywordsnonvolatile
contralateral-gated
neural networks
transition metal dichalcogenide (TMD)
MoS 2
Charge-trap memory
Issue Date2020
Citation
IEEE Electron Device Letters, 2020, v. 41, n. 11, p. 1649-1652 How to Cite?
AbstractThe development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.
Persistent Identifierhttp://hdl.handle.net/10722/297988
ISSN
2023 Impact Factor: 4.1
2023 SCImago Journal Rankings: 1.250
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorChung, Yun Yan-
dc.contributor.authorCheng, Chao Ching-
dc.contributor.authorChou, Yu Che-
dc.contributor.authorChueh, Wei Chen-
dc.contributor.authorChung, Wan Hsuan-
dc.contributor.authorYu, Zhihao-
dc.contributor.authorHung, Terry Yi Tse-
dc.contributor.authorHuang, Lin Yun-
dc.contributor.authorWang, Shin Yuan-
dc.contributor.authorTeng, Li Cheng-
dc.contributor.authorChang, Wen Ho-
dc.contributor.authorLi, Lain Jong-
dc.contributor.authorChien, Chao Hsin-
dc.date.accessioned2021-04-08T03:07:25Z-
dc.date.available2021-04-08T03:07:25Z-
dc.date.issued2020-
dc.identifier.citationIEEE Electron Device Letters, 2020, v. 41, n. 11, p. 1649-1652-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10722/297988-
dc.description.abstractThe development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( text{R}{text {ON}} ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max-min ratio ( {G}{text {MAX}}/ ∼{G}{text {MIN}} ; 50), low nonlinearity of alpha{text {p}} = -0.81 and alpha{text {d}} = -0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.-
dc.languageeng-
dc.relation.ispartofIEEE Electron Device Letters-
dc.subjectnonvolatile-
dc.subjectcontralateral-gated-
dc.subjectneural networks-
dc.subjecttransition metal dichalcogenide (TMD)-
dc.subjectMoS 2-
dc.subjectCharge-trap memory-
dc.titleHigh-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS nFET and Nonvolatile Charge-Trap Memory-
dc.typeArticle-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/LED.2020.3026931-
dc.identifier.scopuseid_2-s2.0-85094871912-
dc.identifier.volume41-
dc.identifier.issue11-
dc.identifier.spage1649-
dc.identifier.epage1652-
dc.identifier.eissn1558-0563-
dc.identifier.isiWOS:000584248800009-
dc.identifier.issnl0741-3106-

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