Showing results 1 to 4 of 4
Title | Author(s) | Issue Date | |
---|---|---|---|
A numerical study of Si-TMD contact with n/p type operation and interface barrier reduction for sub-5 nm monolayer MoS<inf>2</inf> FET Proceeding/Conference:International Electron Devices Meeting (IEDM) | 2017 | ||
First demonstration of 40-nm channel length top-gate WS<inf>2</inf> pFET using channel area-selective CVD growth directly on SiO<inf>x</inf>/Si substrate Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology | 2019 | ||
MoS<inf>2</inf> U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS<inf>2</inf> availability Proceeding/Conference:Digest of Technical Papers - Symposium on VLSI Technology | 2016 | ||
TMD FinFET with 4 nm thin body and back gate control for future low power technology Proceeding/Conference:International Electron Devices Meeting (IEDM) | 2015 |