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- Publisher Website: 10.1109/CASSET.2004.1321960
- Scopus: eid_2-s2.0-20344386251
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Conference Paper: Designing of precomputational-based low-power Viterbi decoder
Title | Designing of precomputational-based low-power Viterbi decoder |
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Authors | |
Issue Date | 2004 |
Publisher | IEEE. |
Citation | The 6th IEEE Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication Proceedings, Shanghai, China, 31 May - 2 June 2004, v. 2, p. 603-606 How to Cite? |
Abstract | This work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%. |
Persistent Identifier | http://hdl.handle.net/10722/46505 |
DC Field | Value | Language |
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dc.contributor.author | Yang, JL | en_HK |
dc.contributor.author | Wong, AKK | en_HK |
dc.date.accessioned | 2007-10-30T06:51:29Z | - |
dc.date.available | 2007-10-30T06:51:29Z | - |
dc.date.issued | 2004 | en_HK |
dc.identifier.citation | The 6th IEEE Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication Proceedings, Shanghai, China, 31 May - 2 June 2004, v. 2, p. 603-606 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/46505 | - |
dc.description.abstract | This work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%. | en_HK |
dc.format.extent | 238954 bytes | - |
dc.format.extent | 5278 bytes | - |
dc.format.extent | 1840 bytes | - |
dc.format.mimetype | application/pdf | - |
dc.format.mimetype | text/plain | - |
dc.format.mimetype | text/plain | - |
dc.language | eng | en_HK |
dc.publisher | IEEE. | en_HK |
dc.rights | ©2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | - |
dc.title | Designing of precomputational-based low-power Viterbi decoder | en_HK |
dc.type | Conference_Paper | en_HK |
dc.description.nature | published_or_final_version | en_HK |
dc.identifier.doi | 10.1109/CASSET.2004.1321960 | - |
dc.identifier.scopus | eid_2-s2.0-20344386251 | - |
dc.identifier.hkuros | 94105 | - |