Exceptional Gate Overvoltage Robustness in P-Gate GaN HEMT with Integrated Circuit Interface

Abstract

The narrow gate overvoltage margin of classical enhancement-mode p-gate GaN high electron mobility transistors (HEMT). is a major concern in both soft and hard switching applications. This work evaluates the gate overvoltage robustness of a smart p-gate GaN HEMT featuring a monolithic IC interface designed to enable a wide range of gate driving voltages (ICeGaN™ HEMT). An external circuit is employed to produce a resonant gate-voltage (VGS) overshoot to characterize the device's VGS boundary under the stress of a single VGS ringing. The ICeGaN™ devices are stressed under different IC biases, at two temperatures (25 and 150 °C), and under two power-loop conditions, i.e., the drain-and-source grounded (DSG) and the 400-V inductive hard switching (HSW). The VGS limit of the ICeGaN™ HEMT is found to be up to 92 V well in excess of that of a discrete classical p-gate GaN HEMT (35 V). The device failure mechanisms under different IC biases are also explored. It is found that, under the dynamic gate overvoltage, the IC interface could re-distribute the surge energy in the driver loop and limit the stress on the gate of the power HEMT. These results show the key role of the monolithic IC in enabling a superior gate overvoltage robustness in ICeGaN™ devices.