Output Capacitance Loss in Wide-bandgap and Superjunction Power Transistors: Impact of Switching Voltage and Current

Abstract

Output capacitance (COSS) loss (EDISS) is a loss recently found to incur in a power semiconductor device when its COSS is charged and discharged, which ideally should be a lossless process. Recent studies have reported considerable EDISS in various power devices when they are utilized in high-frequency soft-switching converters. However, the individual impact of switching voltage (VDS) and current (IDS) has not been fully revealed due to their coupled modulation. This work performs comprehensive experimental characterization of the EDISS of SiC, GaN, and Si superjunction (SJ) transistors, and, for the first time, derives a unified model to describe their EDISS. The individual impact of VDS and IDS on EDISS is revealed for all devices. This model provides device users with quick and useful reference for calculating device EDISS when designing high-frequency soft-switching converters.