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- Publisher Website: 10.1109/CAS59036.2023.10303680
- Scopus: eid_2-s2.0-85178661289
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Conference Paper: Demonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness
Title | Demonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness |
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Authors | |
Keywords | enhancement ESD GaN gate HEMT HTGB HTOL Miller clamp pGaN smart feature threshold voltage |
Issue Date | 2023 |
Citation | Proceedings of the International Semiconductor Conference, CAS, 2023, p. 89-92 How to Cite? |
Abstract | Discrete GaN HEMTs are often perceived as having limited gate voltage range when compared to Silicon and SiC counterparts. Both Schottky and Ohmic pGaN gate devices suffer from low (~1.5 V) threshold voltage, and high gate leakage over 7 V. Their reliability is poor at low temperatures and for gate voltages > 6 V. We have developed an exceptionally robust, smart e-HEMT that boosts both static and dynamic gate reliability, matching or exceeding that of a Silicon IGBT and a SiC MOSFET. In this work, a specially designed setup for evaluating dynamic gate overvoltage limits, finds our GaN e-HEMT to be superior to Silicon and SiC devices. Furthermore, we have (i) demonstrated a high threshold voltage of 2.8 V, (ii) integrated a specially-designed normally-on Miller clamp to enhance immunity to high (> 100 V/ns) dV/dt and dI/dts, (iii) introduced an auxiliary low-to medium voltage HEMT in pass configuration with a clamp attached to its gate to give extra robustness in both static and dynamic conditions (iv) completely removed the need of operating with negative gate voltages, and (v) integrated an electrostatic discharge (ESD) protection circuit to concomitantly protect both the gate and the VDD pin. These devices have also successfully qualified for gate and VDD operation at 20 V through 1000 hours of HTGB/HTOL tests. |
Persistent Identifier | http://hdl.handle.net/10722/352392 |
DC Field | Value | Language |
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dc.contributor.author | Mukherjee, K. | - |
dc.contributor.author | Efthymiou, L. | - |
dc.contributor.author | Ledins, K. | - |
dc.contributor.author | Popa, D. | - |
dc.contributor.author | Wang, B. | - |
dc.contributor.author | Song, Q. | - |
dc.contributor.author | Zhang, Y. | - |
dc.contributor.author | Longobardi, G. | - |
dc.contributor.author | Udrea, F. | - |
dc.date.accessioned | 2024-12-16T03:58:39Z | - |
dc.date.available | 2024-12-16T03:58:39Z | - |
dc.date.issued | 2023 | - |
dc.identifier.citation | Proceedings of the International Semiconductor Conference, CAS, 2023, p. 89-92 | - |
dc.identifier.uri | http://hdl.handle.net/10722/352392 | - |
dc.description.abstract | Discrete GaN HEMTs are often perceived as having limited gate voltage range when compared to Silicon and SiC counterparts. Both Schottky and Ohmic pGaN gate devices suffer from low (~1.5 V) threshold voltage, and high gate leakage over 7 V. Their reliability is poor at low temperatures and for gate voltages > 6 V. We have developed an exceptionally robust, smart e-HEMT that boosts both static and dynamic gate reliability, matching or exceeding that of a Silicon IGBT and a SiC MOSFET. In this work, a specially designed setup for evaluating dynamic gate overvoltage limits, finds our GaN e-HEMT to be superior to Silicon and SiC devices. Furthermore, we have (i) demonstrated a high threshold voltage of 2.8 V, (ii) integrated a specially-designed normally-on Miller clamp to enhance immunity to high (> 100 V/ns) dV/dt and dI/dts, (iii) introduced an auxiliary low-to medium voltage HEMT in pass configuration with a clamp attached to its gate to give extra robustness in both static and dynamic conditions (iv) completely removed the need of operating with negative gate voltages, and (v) integrated an electrostatic discharge (ESD) protection circuit to concomitantly protect both the gate and the VDD pin. These devices have also successfully qualified for gate and VDD operation at 20 V through 1000 hours of HTGB/HTOL tests. | - |
dc.language | eng | - |
dc.relation.ispartof | Proceedings of the International Semiconductor Conference, CAS | - |
dc.subject | enhancement | - |
dc.subject | ESD | - |
dc.subject | GaN | - |
dc.subject | gate | - |
dc.subject | HEMT | - |
dc.subject | HTGB | - |
dc.subject | HTOL | - |
dc.subject | Miller clamp | - |
dc.subject | pGaN | - |
dc.subject | smart feature | - |
dc.subject | threshold voltage | - |
dc.title | Demonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness | - |
dc.type | Conference_Paper | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/CAS59036.2023.10303680 | - |
dc.identifier.scopus | eid_2-s2.0-85178661289 | - |
dc.identifier.spage | 89 | - |
dc.identifier.epage | 92 | - |