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Conference Paper: Demonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness

TitleDemonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness
Authors
Keywordsenhancement
ESD
GaN
gate
HEMT
HTGB
HTOL
Miller clamp
pGaN
smart feature
threshold voltage
Issue Date2023
Citation
Proceedings of the International Semiconductor Conference, CAS, 2023, p. 89-92 How to Cite?
AbstractDiscrete GaN HEMTs are often perceived as having limited gate voltage range when compared to Silicon and SiC counterparts. Both Schottky and Ohmic pGaN gate devices suffer from low (~1.5 V) threshold voltage, and high gate leakage over 7 V. Their reliability is poor at low temperatures and for gate voltages > 6 V. We have developed an exceptionally robust, smart e-HEMT that boosts both static and dynamic gate reliability, matching or exceeding that of a Silicon IGBT and a SiC MOSFET. In this work, a specially designed setup for evaluating dynamic gate overvoltage limits, finds our GaN e-HEMT to be superior to Silicon and SiC devices. Furthermore, we have (i) demonstrated a high threshold voltage of 2.8 V, (ii) integrated a specially-designed normally-on Miller clamp to enhance immunity to high (> 100 V/ns) dV/dt and dI/dts, (iii) introduced an auxiliary low-to medium voltage HEMT in pass configuration with a clamp attached to its gate to give extra robustness in both static and dynamic conditions (iv) completely removed the need of operating with negative gate voltages, and (v) integrated an electrostatic discharge (ESD) protection circuit to concomitantly protect both the gate and the VDD pin. These devices have also successfully qualified for gate and VDD operation at 20 V through 1000 hours of HTGB/HTOL tests.
Persistent Identifierhttp://hdl.handle.net/10722/352392

 

DC FieldValueLanguage
dc.contributor.authorMukherjee, K.-
dc.contributor.authorEfthymiou, L.-
dc.contributor.authorLedins, K.-
dc.contributor.authorPopa, D.-
dc.contributor.authorWang, B.-
dc.contributor.authorSong, Q.-
dc.contributor.authorZhang, Y.-
dc.contributor.authorLongobardi, G.-
dc.contributor.authorUdrea, F.-
dc.date.accessioned2024-12-16T03:58:39Z-
dc.date.available2024-12-16T03:58:39Z-
dc.date.issued2023-
dc.identifier.citationProceedings of the International Semiconductor Conference, CAS, 2023, p. 89-92-
dc.identifier.urihttp://hdl.handle.net/10722/352392-
dc.description.abstractDiscrete GaN HEMTs are often perceived as having limited gate voltage range when compared to Silicon and SiC counterparts. Both Schottky and Ohmic pGaN gate devices suffer from low (~1.5 V) threshold voltage, and high gate leakage over 7 V. Their reliability is poor at low temperatures and for gate voltages > 6 V. We have developed an exceptionally robust, smart e-HEMT that boosts both static and dynamic gate reliability, matching or exceeding that of a Silicon IGBT and a SiC MOSFET. In this work, a specially designed setup for evaluating dynamic gate overvoltage limits, finds our GaN e-HEMT to be superior to Silicon and SiC devices. Furthermore, we have (i) demonstrated a high threshold voltage of 2.8 V, (ii) integrated a specially-designed normally-on Miller clamp to enhance immunity to high (> 100 V/ns) dV/dt and dI/dts, (iii) introduced an auxiliary low-to medium voltage HEMT in pass configuration with a clamp attached to its gate to give extra robustness in both static and dynamic conditions (iv) completely removed the need of operating with negative gate voltages, and (v) integrated an electrostatic discharge (ESD) protection circuit to concomitantly protect both the gate and the VDD pin. These devices have also successfully qualified for gate and VDD operation at 20 V through 1000 hours of HTGB/HTOL tests.-
dc.languageeng-
dc.relation.ispartofProceedings of the International Semiconductor Conference, CAS-
dc.subjectenhancement-
dc.subjectESD-
dc.subjectGaN-
dc.subjectgate-
dc.subjectHEMT-
dc.subjectHTGB-
dc.subjectHTOL-
dc.subjectMiller clamp-
dc.subjectpGaN-
dc.subjectsmart feature-
dc.subjectthreshold voltage-
dc.titleDemonstrating the ICeGaN integrated power HEMT approach towards extreme gate robustness-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/CAS59036.2023.10303680-
dc.identifier.scopuseid_2-s2.0-85178661289-
dc.identifier.spage89-
dc.identifier.epage92-

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