Design Space of Vertical Ga<inf>2</inf>O<inf>3</inf>Junctionless FinFET and its Enhancement with Gradual Channel Doping

Abstract

For the first time, we systematically study the design space of vertical Ga2O3 junctionless FinFET for 600V to 5kV ratings using TCAD simulation with experimentally calibrated parameters. Two scenarios are investigated, namely with "excellent"and "poor"gate oxide/channel interfaces. "Excellent"and "poor"interfaces result in no and severe surface mobility degradation, respectively. It is found that, for the "excellent"case, fin width (W) should be made as small as possible for optimal design. For the "poor"case, optimal W is ~200nm because ION degrades when W < 200nm. However, this can be alleviated by adopting a gradual channel doping scheme, which gives a ~30% boost in ION in the 600V application with a thinned wafer.