Robustness Evaluation and Degradation Mechanisms of SiC MOSFETs Overstressed by Switched Stimuli

Abstract

Evaluation of the robustness of SiC power MOS-FETs outside the safe-operating-area (SOA) conditions is key for their applications in many power electronics applications. Traditional test methods, such as static accelerated lifetime tests, repetitive pulse tests and power cycling, stress devices to excite particular failure mechanisms that do not include all aspects of device operation in industrial switching applications. This work presents a robustness test methodology for SiC MOSFETs, based on switching-based cycling where the switched stimuli (voltage and current) are set to exceed their rated values in each cycle. With the aid of device TCAD simulation and failure analysis, this work, for the first time, reveals the degradation and failure mechanisms of SiC MOSFETs under the out-of-SOA switching cycling tests. Two independent degradation and failure mechanisms have been identified. While the gate-oxide degradation emerges with the increased switching cycles and dominates the ultimate failure of the device, bulk-semiconductor degradation appears simultaneously and drives the device into a partially degraded yet functional state before failure. Changes in electrical parameters over time, including threshold voltage, on-resistance, gate-leakage and drain-leakage currents are all monitored and the precursors for two degradation and failure mechanisms have been identified.