Switching performance evaluation of 1200 v vertical GaN power FinFETs

Abstract

This work evaluates the switching performance of 1.2 kV vertical GaN power FinFETs using the mixed-mode device-circuit TCAD simulation. The device simulation is calibrated with the I-V and C-V characteristics of experimental devices. A double-pulse circuit is implemented in the mixed-mode simulation and subsequently used to evaluate the device turn-on/turn-off times and switching losses under hard switching. To improve the switching performance of vertical power FinFETs, a novel inter-fin design is proposed based on the split-gate geometry. This structure removes the gate metal in the inter-fin region and exposes the drift layer to the source metal. During the device turn-(on)off transients, the drift layer underneath the inter-fin gap region is (dis)charged by the drain-to-source current instead of gate current, leading to shorter switching times and lower switching losses. By utilizing this split-gate structure, over 47% superior switching figure-of-merit (FOM) and over 30% lower switching losses have been demonstrated in 1.2 kV vertical GaN power FinFETs. The 1.2 kV, 80 mΩ split-gate vertical GaN power FinFETs show over 30% superior switching FOM and over 50% smaller switching losses when compared to commercial 1.2 kV SiC MOSFETs under similar switching conditions. These results provide important guidelines for the design of vertical GaN power FinFETs and show their great potentials for high-frequency medium-voltage power applications.