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Conference Paper: Enhancement-mode single-layer CVD MoS2 FET technology for digital electronics

TitleEnhancement-mode single-layer CVD MoS2 FET technology for digital electronics
Authors
Yu, L.El-Damak, D.Ha, S.Ling, X.Lin, Y.Zubair, A.Zhang, Y.Lee, Y. H.Kong, J.Chandrakasan, A.Palacios, T.
Issue Date2015
Citation
Technical Digest - International Electron Devices Meeting, IEDM, 2015, v. 2016-February, p. 32.3.1-32.3.4 How to Cite?
DOI: http://dx.doi.org/10.1109/IEDM.2015.7409814
Abstract2D nanoelectronics based on single-layer (SL) MoS2 offers great advantages for ubiquitous electronics. With new device technology, highly uniform E-mode FETs using SL CVD MoS2 with positive VT, large mobility, excellent subthreshold swing are achieved. The integrated inverter shows excellent voltage transfer characteristic, close to rail-to-rail operation, high noise margin, large voltage gain (∼45) and small static power. The combinational and sequential digital circuits shown here serve as a toolbox of building blocks for realizing wide range of digital circuitry.
Persistent Identifierhttp://hdl.handle.net/10722/352142
ISSN
0163-1918
2023 SCImago Journal Rankings: 1.047

 

DC FieldValueLanguage
dc.contributor.authorYu, L.-
dc.contributor.authorEl-Damak, D.-
dc.contributor.authorHa, S.-
dc.contributor.authorLing, X.-
dc.contributor.authorLin, Y.-
dc.contributor.authorZubair, A.-
dc.contributor.authorZhang, Y.-
dc.contributor.authorLee, Y. H.-
dc.contributor.authorKong, J.-
dc.contributor.authorChandrakasan, A.-
dc.contributor.authorPalacios, T.-
dc.date.accessioned2024-12-16T03:56:57Z-
dc.date.available2024-12-16T03:56:57Z-
dc.date.issued2015-
dc.identifier.citationTechnical Digest - International Electron Devices Meeting, IEDM, 2015, v. 2016-February, p. 32.3.1-32.3.4-
dc.identifier.issn0163-1918-
dc.identifier.urihttp://hdl.handle.net/10722/352142-
dc.description.abstract2D nanoelectronics based on single-layer (SL) MoS2 offers great advantages for ubiquitous electronics. With new device technology, highly uniform E-mode FETs using SL CVD MoS2 with positive VT, large mobility, excellent subthreshold swing are achieved. The integrated inverter shows excellent voltage transfer characteristic, close to rail-to-rail operation, high noise margin, large voltage gain (∼45) and small static power. The combinational and sequential digital circuits shown here serve as a toolbox of building blocks for realizing wide range of digital circuitry.-
dc.languageeng-
dc.relation.ispartofTechnical Digest - International Electron Devices Meeting, IEDM-
dc.titleEnhancement-mode single-layer CVD MoS2 FET technology for digital electronics-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/IEDM.2015.7409814-
dc.identifier.scopuseid_2-s2.0-84964047221-
dc.identifier.volume2016-February-
dc.identifier.spage32.3.1-
dc.identifier.epage32.3.4-

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