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Conference Paper: Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures

TitleCross Layer Design for the Predictive Assessment of Technology-Enabled Architectures
Authors
Keywordsapplication analysis
architectural modeling
circuit modeling
cross-layer design
design space explorations
device modeling
Emerging logic and memory
FeFETs
RRAM
Issue Date2-Jun-2023
PublisherIEEE
Abstract

There is great interest in “end-to-end” analysis that captures how innovation at the materials, device, and/or archi-tectural levels will impact figures of merit at the application-level. However, there are numerous combinations of devices and architectures to study, and we must establish systematic ways to accurately explore and cull a vast design space. We aim to capture how innovations at the materials/device-level may ultimately impact figures of merit associated with both existing and emerging technologies that may be employed for either logic and/or memory. We will highlight how collaborations with researchers at these levels of the design hierarchy - as well as efforts to help construct well-calibrated device models - can in-turn support architectural design space explorations that will help to identify the most promising ways to use new technologies to support application-level workloads of interest. For given compute workloads, we can then quantitatively assess the potential benefits of technology-driven architectures to identify the most promising paths forward. Because of the large number of potentially interesting device-architecture combinations, it is of the utmost importance to develop well-calibrated analytical modeling tools to more rapidly assess the potential value of a given (likely heterogeneous) solution. We highlight recent efforts and needs in this space.


Persistent Identifierhttp://hdl.handle.net/10722/340515
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorNiemier, M-
dc.contributor.authorHu, XS-
dc.contributor.authorLiu, L-
dc.contributor.authorSharifi, M-
dc.contributor.authorO’Connor, Ian-
dc.contributor.authorAtienza, David-
dc.contributor.authorAnsaloni, Giovanni-
dc.contributor.authorLi, Can-
dc.contributor.authorKhan, Asif-
dc.contributor.authorRalph, Daniel C -
dc.date.accessioned2024-03-11T10:45:12Z-
dc.date.available2024-03-11T10:45:12Z-
dc.date.issued2023-06-02-
dc.identifier.urihttp://hdl.handle.net/10722/340515-
dc.description.abstract<p>There is great interest in “end-to-end” analysis that captures how innovation at the materials, device, and/or archi-tectural levels will impact figures of merit at the application-level. However, there are numerous combinations of devices and architectures to study, and we must establish systematic ways to accurately explore and cull a vast design space. We aim to capture how innovations at the materials/device-level may ultimately impact figures of merit associated with both existing and emerging technologies that may be employed for either logic and/or memory. We will highlight how collaborations with researchers at these levels of the design hierarchy - as well as efforts to help construct well-calibrated device models - can in-turn support architectural design space explorations that will help to identify the most promising ways to use new technologies to support application-level workloads of interest. For given compute workloads, we can then quantitatively assess the potential benefits of technology-driven architectures to identify the most promising paths forward. Because of the large number of potentially interesting device-architecture combinations, it is of the utmost importance to develop well-calibrated analytical modeling tools to more rapidly assess the potential value of a given (likely heterogeneous) solution. We highlight recent efforts and needs in this space.<br></p>-
dc.languageeng-
dc.publisherIEEE-
dc.relation.ispartof2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (17/04/2023-19/04/2023, Antwerp)-
dc.subjectapplication analysis-
dc.subjectarchitectural modeling-
dc.subjectcircuit modeling-
dc.subjectcross-layer design-
dc.subjectdesign space explorations-
dc.subjectdevice modeling-
dc.subjectEmerging logic and memory-
dc.subjectFeFETs-
dc.subjectRRAM-
dc.titleCross Layer Design for the Predictive Assessment of Technology-Enabled Architectures-
dc.typeConference_Paper-
dc.identifier.doi10.23919/DATE56975.2023.10136923-
dc.identifier.scopuseid_2-s2.0-85162722401-
dc.identifier.volume2023-April-
dc.identifier.isiWOS:001027444200027-

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