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Conference Paper: Fabrication and electrical performance of CVD-grown MoS2 transistor

TitleFabrication and electrical performance of CVD-grown MoS2 transistor
Authors
Wen, MXu, JPLiu, LZhao, XLai, PTTang, WM
KeywordsBuffer layer
Carrier mobility
CVD
MoS2 transistor
Issue Date2017
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853
Citation
2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 18-20 October 2017, p. 1-3 How to Cite?
DOI: http://dx.doi.org/10.1109/EDSSC.2017.8126502
AbstractA 6-layer continuous and uniform MoS 2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS 2 transistor are investigated, and enhanced carrier mobility (0.69 cm 2 /V·s) is achieved by using Ta 2 O 5 as the buffer layer.
Persistent Identifierhttp://hdl.handle.net/10722/278340
ISBN
978-1-5386-2908-6

 

DC FieldValueLanguage
dc.contributor.authorWen, M-
dc.contributor.authorXu, JP-
dc.contributor.authorLiu, L-
dc.contributor.authorZhao, X-
dc.contributor.authorLai, PT-
dc.contributor.authorTang, WM-
dc.date.accessioned2019-10-04T08:12:06Z-
dc.date.available2019-10-04T08:12:06Z-
dc.date.issued2017-
dc.identifier.citation2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, 18-20 October 2017, p. 1-3-
dc.identifier.isbn978-1-5386-2908-6-
dc.identifier.urihttp://hdl.handle.net/10722/278340-
dc.description.abstractA 6-layer continuous and uniform MoS 2 film is successfully grown by thermal chemical vapor deposition (CVD) through optimizing its growth conditions, and is used as channel material to fabricate top-gated transistors by conventional lithography process. Also, the effects of a buffer layer on the electrical performance of the CVD MoS 2 transistor are investigated, and enhanced carrier mobility (0.69 cm 2 /V·s) is achieved by using Ta 2 O 5 as the buffer layer.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000853-
dc.relation.ispartofIEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)-
dc.rightsIEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). Copyright © IEEE.-
dc.rights©2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectBuffer layer-
dc.subjectCarrier mobility-
dc.subjectCVD-
dc.subjectMoS2 transistor-
dc.titleFabrication and electrical performance of CVD-grown MoS2 transistor-
dc.typeConference_Paper-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.identifier.doi10.1109/EDSSC.2017.8126502-
dc.identifier.scopuseid_2-s2.0-85043489987-
dc.identifier.hkuros306917-
dc.identifier.spage1-
dc.identifier.epage3-
dc.publisher.placeUnited States-

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