Towards Flexible Automatic Generation of Graph Processing Gateware

Abstract

FPGAs have been demonstrated as promising platforms to accelerate graph processing applications at scale with superior energy-efficiency. However, programming FPGAs is significantly more challenging than similar software solutions. To address this productivity challenge, several graph processing frameworks for FPGA have already been proposed in recent years. These frameworks aim to lower a programmerâĂŹs burden by requiring users to provide only logic specific to the target graph algorithm, while leaving the auto generation of the rest of the hardware design to the framework. In this work, we extend the capability of the GraVF framework and improve the scale of its supported input graphs by a) making the synchronization method independent of the network structure and b) adding support for off-chip memory. The improved system accepts graph sizes an order of magnitude larger than previously reported and provides throughput in the order of 100MTEPS per processing element.