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Conference Paper: Interfacial and Electrical Properties of Ge MOS Capacitor by ZrLaON Passivation Layer and Fluorine Incorporation

TitleInterfacial and Electrical Properties of Ge MOS Capacitor by ZrLaON Passivation Layer and Fluorine Incorporation
Authors
Issue Date2017
PublisherInstitute of Physics Publishing Ltd. The Journal's web site is located at http://iopscience.iop.org/1757-899X/
Citation
2nd International Conference on Advanced Materials Research and Manufacturing Technologies (AMRMT 2017), Phuket, Thailand, 2–5 August 2017. In IOP Conference Series: Materials Science and Engineering, 2017 , v. 229, article no. 012018 How to Cite?
AbstractGe Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm−2eV−1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10−5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.
Persistent Identifierhttp://hdl.handle.net/10722/262433
ISSN
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorHuang, Y-
dc.contributor.authorXu, JP-
dc.contributor.authorLiu, L-
dc.contributor.authorCheng, ZX-
dc.contributor.authorLai, PT-
dc.contributor.authorTang, WM-
dc.date.accessioned2018-09-28T04:59:15Z-
dc.date.available2018-09-28T04:59:15Z-
dc.date.issued2017-
dc.identifier.citation2nd International Conference on Advanced Materials Research and Manufacturing Technologies (AMRMT 2017), Phuket, Thailand, 2–5 August 2017. In IOP Conference Series: Materials Science and Engineering, 2017 , v. 229, article no. 012018-
dc.identifier.issn1757-8981-
dc.identifier.urihttp://hdl.handle.net/10722/262433-
dc.description.abstractGe Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm−2eV−1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10−5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.-
dc.languageeng-
dc.publisherInstitute of Physics Publishing Ltd. The Journal's web site is located at http://iopscience.iop.org/1757-899X/-
dc.relation.ispartofIOP Conference Series: Materials Science and Engineering-
dc.rightsIOP Conference Series: Materials Science and Engineering. Copyright © Institute of Physics Publishing Ltd.-
dc.titleInterfacial and Electrical Properties of Ge MOS Capacitor by ZrLaON Passivation Layer and Fluorine Incorporation-
dc.typeConference_Paper-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.description.naturelink_to_OA_fulltext-
dc.identifier.doi10.1088/1757-899X/229/1/012018-
dc.identifier.scopuseid_2-s2.0-85033783911-
dc.identifier.hkuros292232-
dc.identifier.volume229-
dc.identifier.spage012018-
dc.identifier.epage012018-
dc.identifier.isiWOS:000419254500018-
dc.publisher.placeUnited Kingdom-
dc.identifier.issnl1757-8981-

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