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- Publisher Website: 10.1109/ICSICT.2014.7021197
- Scopus: eid_2-s2.0-84946689033
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Conference Paper: A chip-level transient electro-thermal field simulator with gate capacitance and matrix exponential
Title | A chip-level transient electro-thermal field simulator with gate capacitance and matrix exponential |
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Authors | |
Issue Date | 2014 |
Publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000707 |
Citation | The 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014), Guilin, China, 28-31 October 2014. In Conference Proceedings, 2014, p. 1-4 How to Cite? |
Abstract | This paper presents a new transient electro-thermal (ET) simulation method for fast 3D chip-level analysis of power electronics with field solver accuracy. The metallization stacks are meshed and solved with 3D field solver using nonlinear temperature-dependent electrical and thermal parameters, and the active transistors are modeled with compact models to avoid time-consuming TCAD simulation. Two new ingredients are introduced to further enhance physical relevance and computational performance: 1) Gate capacitance of power MOS is explicitly accounted for in the electrical subsystem to improve the modeling accuracy for power devices with large summed gate capacitance; 2) To address the considerably different time scales between electrical and thermal sectors, the electrical system is solved by the matrix exponential method (MEXP), which allows larger time step sizes without sacrificing accuracy and thus accelerates the ET coupled simulation. © 2014 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/216396 |
ISBN |
DC Field | Value | Language |
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dc.contributor.author | Mei, Q | - |
dc.contributor.author | Wong, N | - |
dc.contributor.author | Chen, Q | - |
dc.date.accessioned | 2015-09-18T05:26:20Z | - |
dc.date.available | 2015-09-18T05:26:20Z | - |
dc.date.issued | 2014 | - |
dc.identifier.citation | The 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014), Guilin, China, 28-31 October 2014. In Conference Proceedings, 2014, p. 1-4 | - |
dc.identifier.isbn | 978-1-4799-3282-5 | - |
dc.identifier.uri | http://hdl.handle.net/10722/216396 | - |
dc.description.abstract | This paper presents a new transient electro-thermal (ET) simulation method for fast 3D chip-level analysis of power electronics with field solver accuracy. The metallization stacks are meshed and solved with 3D field solver using nonlinear temperature-dependent electrical and thermal parameters, and the active transistors are modeled with compact models to avoid time-consuming TCAD simulation. Two new ingredients are introduced to further enhance physical relevance and computational performance: 1) Gate capacitance of power MOS is explicitly accounted for in the electrical subsystem to improve the modeling accuracy for power devices with large summed gate capacitance; 2) To address the considerably different time scales between electrical and thermal sectors, the electrical system is solved by the matrix exponential method (MEXP), which allows larger time step sizes without sacrificing accuracy and thus accelerates the ET coupled simulation. © 2014 IEEE. | - |
dc.language | eng | - |
dc.publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000707 | - |
dc.relation.ispartof | International Conference on Solid-State and Integrated Circuit Technology Proceedings | - |
dc.rights | International Conference on Solid-State and Integrated Circuit Technology Proceedings. Copyright © IEEE. | - |
dc.rights | ©2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.title | A chip-level transient electro-thermal field simulator with gate capacitance and matrix exponential | - |
dc.type | Conference_Paper | - |
dc.identifier.email | Wong, N: nwong@eee.hku.hk | - |
dc.identifier.email | Chen, Q: q1chen@hku.hk | - |
dc.identifier.authority | Wong, N=rp00190 | - |
dc.identifier.authority | Chen, Q=rp01688 | - |
dc.description.nature | link_to_OA_fulltext | - |
dc.identifier.doi | 10.1109/ICSICT.2014.7021197 | - |
dc.identifier.scopus | eid_2-s2.0-84946689033 | - |
dc.identifier.hkuros | 253338 | - |
dc.identifier.spage | 1 | - |
dc.identifier.epage | 4 | - |
dc.publisher.place | United States | - |
dc.customcontrol.immutable | sml 151119 | - |