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Conference Paper: Logic simulation with interval-labelled net model

TitleLogic simulation with interval-labelled net model
Authors
Issue Date1989
Citation
Proceedings of the 3rd International Workshop on Petri Nets and Performance Models (PNPM'89), Kyoto, Japan, 11-13 December 1989. How to Cite?
AbstractA novel approach to the application of an interval-labeled net model in logic simulation with timing among concurrent processes is introduced. By means of the model, logic circuit properties involving timing information can be specified and simulated in a multiprocessor-based environment using the token-passing algorithm. A logic simulator with timing information with a structure based on this approach is proposed.
Persistent Identifierhttp://hdl.handle.net/10722/158057
References

 

DC FieldValueLanguage
dc.contributor.authorChiu, Peter PKen_US
dc.contributor.authorCheung, YSen_US
dc.date.accessioned2012-08-08T08:57:54Z-
dc.date.available2012-08-08T08:57:54Z-
dc.date.issued1989en_US
dc.identifier.citationProceedings of the 3rd International Workshop on Petri Nets and Performance Models (PNPM'89), Kyoto, Japan, 11-13 December 1989.-
dc.identifier.urihttp://hdl.handle.net/10722/158057-
dc.description.abstractA novel approach to the application of an interval-labeled net model in logic simulation with timing among concurrent processes is introduced. By means of the model, logic circuit properties involving timing information can be specified and simulated in a multiprocessor-based environment using the token-passing algorithm. A logic simulator with timing information with a structure based on this approach is proposed.en_US
dc.languageengen_US
dc.relation.ispartofInternational Workshop on Petri Nets and Performance Models Proceedings-
dc.titleLogic simulation with interval-labelled net modelen_US
dc.typeConference_Paperen_US
dc.identifier.emailCheung, YS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, YS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0024914667en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0024914667&selection=ref&src=s&origin=recordpage-
dc.identifier.scopusauthoridChiu, Peter PK=7103182574en_US
dc.identifier.scopusauthoridCheung, YS=7202595335en_US
dc.customcontrol.immutablesml 151028 - meregd-

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