EFFICIENT IMAGE CONVOLUTION USING VLSI.

Abstract

The aim of this work is to provide a practical solution to the computation intensive convolution task in image processing which may cope with the amount of low-level processing on high-resolution inputs, and to offer a cost effective number crunching subsystem to industrial image processing systems. The convolution architecture is derived from a recursive methodology which offers extremely high concurrency in the form of hierarchies and the flexibility of either increasing the size and/or the input/output bandwidth of the convolver on chip or off chip. The concurrency of the convolver is the major factor of the speeding-up of the computation, and the flexibility of the architecture makes system implementation and matching much easier. Although the methodology is more for VLSI technology, a TTL prototype system using a 3-by-3 convolver board has been built and is running at 60-ns cycle time for real-time applications on images up to 512 by 512. The concept of the convolution architecture and the VLSI version are discussed.