CONSTRAINED DECOMPOSITION OF BINARY ADDITION FOR VLSI SIGNAL/IMAGE PROCESSING.

Abstract

The constrained decomposition of binary addition is presented for real-time VLSI signal and image processing (SIP), resulting in a high-speed parallel adder design with regular, modular and concurrent architecture with a very local and compact communication network. Its inherent pipelining feature requires straightforward clocking and its recursive structure offers word-size expansion and embedding into a high-level procedural description. The optimality of the addition algorithm is determined by a small (i. e. , 2) global branching ratio greater than 1 and a variable local branching ratio in terms of its cost-performance function. This architectural feature enables a much larger data set and longer word size to be used to design SIP systems with high accuracy and resolution. VLSI implementation and comparison of the algorithm's performance with carry propagate and carry lookahead addition are presented.