PROGRAMMABLE VLSI ARRAY PROCESSOR SYSTEM FOR IIR/FIR DIGITAL FILTERING.

Abstract

A novel VLSI (Very Large Scale Integration) architecture for real time IIR (Infinite Impulse Response) and FIR (Finite Impulse Response) filtering with programmable filter length and coefficients is presented. The filter array utilizes the 1-D two-way pipelined systolic algorithm with highly regular and modular structure offering extensive pipelining facility. Its compact and local communication geometry enables the array to be mapped into present and future VLSI technology efficiently. The implementation of a floating point array processing element based on a recursive multiplication/addition algorithm is described together with its cost- performance analysis and comparison with the conventional parallel designs. A M68000 based control system which provides all the complex control and initialization sequences as well as a user friendly programming environment is also considered.