File Download
  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: Optimization of N content for higk-k LaTiON gate dielectric of Ge MOS capacitor

TitleOptimization of N content for higk-k LaTiON gate dielectric of Ge MOS capacitor
Authors
Xu, HXXu, JPLi, CXLiu, LLai, PTChan, CL
KeywordsC-V hysteresis
Capacitance-equivalent thickness
Electrical characteristic
Electrical property
Gate-leakage current
Issue Date2009
PublisherIEEE.
Citation
The IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 225-228 How to Cite?
DOI: http://dx.doi.org/10.1109/EDSSC.2009.5394279
AbstractThin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La 2O 3 and Ti targets under different Ar/N 2 ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N 2 ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO x interfacial layer between LaTiON and Ge substrate.
Persistent Identifierhttp://hdl.handle.net/10722/126170
ISBN
978-1-4244-4297-3
ISI Accession Number ID
WOS:000289818000057
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorXu, HXen_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorLi, CXen_HK
dc.contributor.authorLiu, Len_HK
dc.contributor.authorLai, PTen_HK
dc.contributor.authorChan, CLen_HK
dc.date.accessioned2010-10-31T12:13:35Z-
dc.date.available2010-10-31T12:13:35Z-
dc.date.issued2009en_HK
dc.identifier.citationThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 225-228en_HK
dc.identifier.isbn978-1-4244-4297-3-
dc.identifier.urihttp://hdl.handle.net/10722/126170-
dc.description.abstractThin LaTiON gate dielectric is deposited on Ge (100) substrate by reactive co-sputtering of La 2O 3 and Ti targets under different Ar/N 2 ratios of 24/3, 24/6, 24/12, and 24/18, and their electrical properties are investigated and compared. Results show that the LaTiON gate-dielectric Ge MOS capacitor prepared at an Ar/N 2 ratio of 24/6 exhibits highest relative permittivity, smallest capacitance equivalent thickness, and best electrical characteristics, including low interface-state density, small C-V hysteresis and low gate leakage current. This is attributed to the fact that a suitable N content in LaTiON can effectively suppress the growth of low-k GeO x interfacial layer between LaTiON and Ge substrate.en_HK
dc.languageengen_HK
dc.publisherIEEE.-
dc.relation.ispartof2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009en_HK
dc.rights©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectC-V hysteresis-
dc.subjectCapacitance-equivalent thickness-
dc.subjectElectrical characteristic-
dc.subjectElectrical property-
dc.subjectGate-leakage current-
dc.titleOptimization of N content for higk-k LaTiON gate dielectric of Ge MOS capacitoren_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=978-1-4244-4297-3&volume=&spage=225&epage=228&date=2009&atitle=Optimization+of+N+content+for+higk-k+LaTiON+gate+dielectric+of+Ge+MOS+capacitor-
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/EDSSC.2009.5394279en_HK
dc.identifier.scopuseid_2-s2.0-77949650159en_HK
dc.identifier.hkuros180680en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77949650159&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage225en_HK
dc.identifier.epage228en_HK
dc.identifier.isiWOS:000289818000057-
dc.description.otherThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 225-228-
dc.identifier.scopusauthoridXu, HX=25639287800en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridLi, CX=22034888200en_HK
dc.identifier.scopusauthoridLiu, L=35778603700en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK
dc.identifier.scopusauthoridChan, CL=8507083700en_HK

Export via OAI-PMH Interface in XML Formats

OR

Export to Other Non-XML Formats