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Conference Paper: A compact threshold-voltage model of MOSFETs with stack high-k gate dielectric

TitleA compact threshold-voltage model of MOSFETs with stack high-k gate dielectric
Authors
Ji, FXu, JPChen, JJXu, HXLi, CXLai, PT
KeywordsMOSFET
Stack gate dielectric
Threshold voltage
Issue Date2009
PublisherIEEE.
Citation
The IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xian, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 236-239 How to Cite?
DOI: http://dx.doi.org/10.1109/EDSSC.2009.5394286
AbstractIn this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interiayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interiayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current. ©2009 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/126039
ISBN
978-1-4244-4297-3
ISI Accession Number ID
WOS:000289818000060
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorJi, Fen_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorChen, JJen_HK
dc.contributor.authorXu, HXen_HK
dc.contributor.authorLi, CXen_HK
dc.contributor.authorLai, PTen_HK
dc.date.accessioned2010-10-31T12:06:29Z-
dc.date.available2010-10-31T12:06:29Z-
dc.date.issued2009en_HK
dc.identifier.citationThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xian, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 236-239en_HK
dc.identifier.isbn978-1-4244-4297-3-
dc.identifier.urihttp://hdl.handle.net/10722/126039-
dc.description.abstractIn this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interiayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interiayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current. ©2009 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.-
dc.relation.ispartof2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009en_HK
dc.rights©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectMOSFETen_HK
dc.subjectStack gate dielectricen_HK
dc.subjectThreshold voltageen_HK
dc.titleA compact threshold-voltage model of MOSFETs with stack high-k gate dielectricen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=978-1-4244-4297-3&volume=&spage=236&epage=239&date=2009&atitle=A+compact+threshold-voltage+model+of+MOSFETs+with+stack+High-k+gate+dielectric-
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/EDSSC.2009.5394286en_HK
dc.identifier.scopuseid_2-s2.0-77949608657en_HK
dc.identifier.hkuros180687en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77949608657&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage236en_HK
dc.identifier.epage239en_HK
dc.identifier.isiWOS:000289818000060-
dc.description.otherThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xian, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 236-239-
dc.identifier.scopusauthoridJi, F=8238553900en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridChen, JJ=7501878473en_HK
dc.identifier.scopusauthoridXu, HX=25639287800en_HK
dc.identifier.scopusauthoridLi, CX=22034888200en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK

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