Gate screening effect on remote phonon scattering in MOS-based transistors

Abstract

Semiconductor devices are increasingly adopting high-k gate dielectrics over traditional SiO2 for enhanced miniaturization and performance. However, high-k materials introduce strong remote phonon scattering (RPS) due to their severe vibration of highly-polarizable metal-oxygen bonds, which degrades the channel-carrier mobility. Gate-electrode plasmons, generated by charge-carrier oscillation about ion, can suppress the RPS by electrically coupling with the gate-dielectric phonons (so called gate screening effect) to improve the channel-carrier mobility. Therefore, this thesis systematically explores this gate screening mechanism on the RPS in both n-channel InGaZnO (IGZO) TFTs and p-channel pentacene TFTs, providing insights on enhancing the performance of MOS-based transistors with high-k gate dielectrics. Firstly, the impact of gate-dielectric annealing temperature on the channel-carrier mobility of IGZO TFT is studied. Experimental results show that the carrier mobility generally decreases with increasing annealing temperature, which can be attributed to the formation of a thicker silicate interlayer between the gate dielectric and the gate electrode during higher-temperature annealing, leading to a larger separation between gate-electrode plasmons and gate-dielectric phonons and thus a weaker gate screening effect on the RPS. Secondly, IGZO TFTs with various SiO2 thicknesses in double-layered high-k gate dielectric (NdHfO/SiO2) and different hole concentrations in gate electrode are fabricated to systematically study the influence of the gate-electrode/gate-dielectric SiO2 interlayer on the gate screening effect. Channel-carrier mobility increases with the rise of gate hole concentration and the decrease of SiO2 interlayer thickness due to generation of more gate plasmons and stronger electrical coupling between them and gate-dielectric phonons, respectively. Thirdly, IGZO TFTs with 10 different gate hole concentrations are fabricated to investigate the influence of the low-k SiO2 layer in double-layered high-k gate dielectric (NdHfO/SiO2) on the gate anti-screening effect. For two gate hole concentrations, the emergence of large channel-mobility reduction caused by the resonance between the relatively-rigid SiO2 and the adjacent gate electrode (thus greatly-enhanced RPS) is observed, demonstrating that the low-k layer in a double-layered high-k gate dielectric can also have significant effects on the RPS and thus carrier mobility in MOS devices. Fourthly, semiconductors (n-Si, n-Ge, n-GaAs, ITO) with various electron concentrations are applied as gate electrodes of p-channel pentacene OTFTs with HfLaON as high-k gate dielectric. For the same gate electron concentration, the channel-carrier mobility of the n-GaAs-gate device is higher than those of its n-Ge-gate and n-Si-gate counterparts because gate electrode with lower effective electron mass produces higher-energy gate plasmons that can better suppress the RPS. Finally, pentacene OTFTs with HfLaON high-k gate dielectric have been fabricated using various metals for gate electrode, including Al, Au, Cu, Cr, Ti and Pt. Despite having similar pentacene grain size and gate-dielectric surface roughness, the Ti-gate sample obtains the highest channel-carrier mobility of 9.21 cm2V-1s-1. This can be attributed to its highest gate plasmon energy (resulted from both high gate electron concentration and low gate effective electron mass), which generates the strongest gate screening effect on the RPS.