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- Publisher Website: 10.1109/TNB.2013.2294943
- Scopus: eid_2-s2.0-84896298648
- PMID: 24594509
- WOS: WOS:000332735300002
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Article: Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect
Title | Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect |
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Authors | |
Keywords | Contamination defect lab-on-a-chip design automation physical-level synthesis variation |
Issue Date | 2014 |
Citation | IEEE Transactions on Nanobioscience, 2014, v. 13, n. 1, p. 3-11 How to Cite? |
Abstract | Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique. © 2002-2011 IEEE. |
Persistent Identifier | http://hdl.handle.net/10722/336122 |
ISSN | 2023 Impact Factor: 3.7 2023 SCImago Journal Rankings: 0.659 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Liao, Chen | - |
dc.contributor.author | Hu, Shiyan | - |
dc.date.accessioned | 2024-01-15T08:23:40Z | - |
dc.date.available | 2024-01-15T08:23:40Z | - |
dc.date.issued | 2014 | - |
dc.identifier.citation | IEEE Transactions on Nanobioscience, 2014, v. 13, n. 1, p. 3-11 | - |
dc.identifier.issn | 1536-1241 | - |
dc.identifier.uri | http://hdl.handle.net/10722/336122 | - |
dc.description.abstract | Microfluidic lab-on-a-chips have been widely utilized in biochemical analysis and human health studies due to high detection accuracy, high timing efficiency, and low cost. The increasing design complexity of lab-on-a-chips necessitates the computer-aided design (CAD) methodology in contrast to the classical manual design methodology. A key part in lab-on-a-chip CAD is physical-level synthesis. It includes the lab-on-a-chip placement and routing, where placement is to determine the physical location and the starting time of each operation and routing is to transport each droplet from the source to the destination. In the lab-on-a-chip design, variation, contamination, and defect need to be considered. This work designs a physical-level synthesis flow which simultaneously considers variation, contamination, and defect of the lab-on-a-chip design. It proposes a maze routing based, variation, contamination, and defect aware droplet routing technique, which is seamlessly integrated into an existing placement technique. The proposed technique improves the placement solution for routing and achieves the placement and routing co-optimization to handle variation, contamination, and defect. The simulation results demonstrate that our technique does not use any defective/contaminated grids, while the technique without considering contamination and defect uses 17.0% of the defective/contaminated grids on average. In addition, our routing variation aware technique significantly improves the average routing yield by 51.2% with only 3.5% increase in completion time compared to a routing variation unaware technique. © 2002-2011 IEEE. | - |
dc.language | eng | - |
dc.relation.ispartof | IEEE Transactions on Nanobioscience | - |
dc.subject | Contamination | - |
dc.subject | defect | - |
dc.subject | lab-on-a-chip design automation | - |
dc.subject | physical-level synthesis | - |
dc.subject | variation | - |
dc.title | Physical-level synthesis for digital lab-on-a-chip considering variation, contamination, and defect | - |
dc.type | Article | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/TNB.2013.2294943 | - |
dc.identifier.pmid | 24594509 | - |
dc.identifier.scopus | eid_2-s2.0-84896298648 | - |
dc.identifier.volume | 13 | - |
dc.identifier.issue | 1 | - |
dc.identifier.spage | 3 | - |
dc.identifier.epage | 11 | - |
dc.identifier.isi | WOS:000332735300002 | - |