Discrete wavelet transform based circuit layout fingerprinting using chaotic system

Abstract

Tight time-to-market pressure requires CAD tools to heavily involve component reuse, or intellectual property (IP) reuse, which imposes intense security concerns on IP protection. For the IP providers, it is critical to protect their products against unauthorized reproduction. Thus, circuit layout fingerprinting becomes quite important which helps the IP providers to detect which user distributes the illegal IPs. However, previous works addressing the circuit fingerprinting all have large area and runtime overhead. In this paper, a novel efficient discrete wavelet transform (DWT)-based key sensitive circuit layout fingerprinting technique using chaotic system is proposed. The new circuit layout fingerprinting technique targets to be applied after placement and routing, while before fabrication. Thus, it only slightly impacts the original design and introduces small runtime overhead as well. To further enhance the security, the chaotic system based on Fibonacci transformation is integrated. The experimental results demonstrate that our chaotic DWT-based technique largely outperforms a median-based technique for various attacks. The chaotic DWT-based technique improves the detection error rate by 68.5% for the gate swapping attack, by 65.8% for the random perturbation attack, by 54.8% for the partition-based perturbation attack and by 54.5% for the combined perturbation attack. In addition, the average wirelength overhead is only 0.0149% compared to the original design and the average runtime overhead is only 6.73 s. These demonstrate the effectiveness of our circuit layout fingerprinting technique. © 2012 World Scientific Publishing Company.