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- Publisher Website: 10.1145/1735023.1735047
- Scopus: eid_2-s2.0-77952286035
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Conference Paper: Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Title | Ultra-fast interconnect driven cell cloning for minimizing critical path delay |
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Authors | |
Keywords | Gate duplication Physical synthesis Timing-driven placement |
Issue Date | 2010 |
Citation | Proceedings of the International Symposium on Physical Design, 2010, p. 75-82 How to Cite? |
Abstract | In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say nothing of efficiency. This work explores innovative cloning (gate duplication) techniques to improve timing-closure in a physical synthesis environment. With a buffer-aware interconnect timing model, new polynomial-time optimal algorithms are proposed for timing-driven cloning, including both finding optimal sink partitions (identifying the fan-outs) for the original and the duplicated gates, as well as physical locations for both gates. In particular, we present an O(m)-time optimal algorithm to minimize the worst slack if the original gate is movable, and an O(m log m) algorithm if the original gate is fixed, where $m$ is the number of fan-outs. To the best of our knowledge, this work is the first one considering the timing-driven cloning problem under a buffer-aware interconnect delay model. For a hundred testcases in 45nm technology node, we demonstrate significant timing improvement due to our cloning techniques as compared to other existing timing-optimization transforms. Extensions to other factors, such as wirelength, FOM and placement obstacles are further discussed. Copyright 2010 ACM. |
Persistent Identifier | http://hdl.handle.net/10722/336082 |
DC Field | Value | Language |
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dc.contributor.author | Li, Zhuo | - |
dc.contributor.author | Papa, David A. | - |
dc.contributor.author | Alpert, Charles J. | - |
dc.contributor.author | Hu, Shiyan | - |
dc.contributor.author | Shi, Weiping | - |
dc.contributor.author | Sze, Cliff | - |
dc.contributor.author | Zhou, Ying | - |
dc.date.accessioned | 2024-01-15T08:23:16Z | - |
dc.date.available | 2024-01-15T08:23:16Z | - |
dc.date.issued | 2010 | - |
dc.identifier.citation | Proceedings of the International Symposium on Physical Design, 2010, p. 75-82 | - |
dc.identifier.uri | http://hdl.handle.net/10722/336082 | - |
dc.description.abstract | In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say nothing of efficiency. This work explores innovative cloning (gate duplication) techniques to improve timing-closure in a physical synthesis environment. With a buffer-aware interconnect timing model, new polynomial-time optimal algorithms are proposed for timing-driven cloning, including both finding optimal sink partitions (identifying the fan-outs) for the original and the duplicated gates, as well as physical locations for both gates. In particular, we present an O(m)-time optimal algorithm to minimize the worst slack if the original gate is movable, and an O(m log m) algorithm if the original gate is fixed, where $m$ is the number of fan-outs. To the best of our knowledge, this work is the first one considering the timing-driven cloning problem under a buffer-aware interconnect delay model. For a hundred testcases in 45nm technology node, we demonstrate significant timing improvement due to our cloning techniques as compared to other existing timing-optimization transforms. Extensions to other factors, such as wirelength, FOM and placement obstacles are further discussed. Copyright 2010 ACM. | - |
dc.language | eng | - |
dc.relation.ispartof | Proceedings of the International Symposium on Physical Design | - |
dc.subject | Gate duplication | - |
dc.subject | Physical synthesis | - |
dc.subject | Timing-driven placement | - |
dc.title | Ultra-fast interconnect driven cell cloning for minimizing critical path delay | - |
dc.type | Conference_Paper | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1145/1735023.1735047 | - |
dc.identifier.scopus | eid_2-s2.0-77952286035 | - |
dc.identifier.spage | 75 | - |
dc.identifier.epage | 82 | - |