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- Publisher Website: 10.5370/JEET.2016.11.1.143
- Scopus: eid_2-s2.0-85010876950
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Article: Half load-cycle worked dual SEPIC single-stage inverter
Title | Half load-cycle worked dual SEPIC single-stage inverter |
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Authors | |
Keywords | Half load-cycle worked SEPIC Single-stage inverter SPWM |
Issue Date | 2016 |
Citation | Journal of Electrical Engineering and Technology, 2016, v. 11, n. 1, p. 143-149 How to Cite? |
Abstract | The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter. |
Persistent Identifier | http://hdl.handle.net/10722/318651 |
ISSN | 2023 Impact Factor: 1.6 2023 SCImago Journal Rankings: 0.434 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | Chen, Rong | - |
dc.contributor.author | Zhang, Jia Sheng | - |
dc.contributor.author | Liu, Wei | - |
dc.contributor.author | Zheng, Chang Ming | - |
dc.date.accessioned | 2022-10-11T12:24:15Z | - |
dc.date.available | 2022-10-11T12:24:15Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | Journal of Electrical Engineering and Technology, 2016, v. 11, n. 1, p. 143-149 | - |
dc.identifier.issn | 1975-0102 | - |
dc.identifier.uri | http://hdl.handle.net/10722/318651 | - |
dc.description.abstract | The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter. | - |
dc.language | eng | - |
dc.relation.ispartof | Journal of Electrical Engineering and Technology | - |
dc.subject | Half load-cycle worked | - |
dc.subject | SEPIC | - |
dc.subject | Single-stage inverter | - |
dc.subject | SPWM | - |
dc.title | Half load-cycle worked dual SEPIC single-stage inverter | - |
dc.type | Article | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.5370/JEET.2016.11.1.143 | - |
dc.identifier.scopus | eid_2-s2.0-85010876950 | - |
dc.identifier.volume | 11 | - |
dc.identifier.issue | 1 | - |
dc.identifier.spage | 143 | - |
dc.identifier.epage | 149 | - |
dc.identifier.eissn | 2093-7423 | - |
dc.identifier.isi | WOS:000367637300017 | - |