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Conference Paper: Variational analog integrated circuit design via symbolic sensitivity analysis

TitleVariational analog integrated circuit design via symbolic sensitivity analysis
Authors
KeywordsAnalog circuit design
Binary decision diagram
Design optimization
Graph reduction
Symbolic AC sensitivity
Issue Date2009
Citation
Proceedings - IEEE International Symposium on Circuits and Systems, 2009, p. 3002-3005 How to Cite?
AbstractThis paper presents a symbolic AC sensitivity analysis technique using a graph-reduction based symbolic simulator GRASS. Symbolic sum-of-products are derived from a graph reduction process and represented by a binary decision diagram. The GRASS simulator maintains a one-to-one correspondence between the circuit parameters and the simulator symbols, with which differentiating the frequency response with respect to any circuit parameter becomes straightforward. The implementation details of symbolic AC sensitivity are presented and the potential applications are demonstrated. ©2009 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/315219
ISSN
2023 SCImago Journal Rankings: 0.307

 

DC FieldValueLanguage
dc.contributor.authorShi, Guoyong-
dc.contributor.authorMeng, Xiaoxuan-
dc.date.accessioned2022-08-05T10:18:06Z-
dc.date.available2022-08-05T10:18:06Z-
dc.date.issued2009-
dc.identifier.citationProceedings - IEEE International Symposium on Circuits and Systems, 2009, p. 3002-3005-
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10722/315219-
dc.description.abstractThis paper presents a symbolic AC sensitivity analysis technique using a graph-reduction based symbolic simulator GRASS. Symbolic sum-of-products are derived from a graph reduction process and represented by a binary decision diagram. The GRASS simulator maintains a one-to-one correspondence between the circuit parameters and the simulator symbols, with which differentiating the frequency response with respect to any circuit parameter becomes straightforward. The implementation details of symbolic AC sensitivity are presented and the potential applications are demonstrated. ©2009 IEEE.-
dc.languageeng-
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systems-
dc.subjectAnalog circuit design-
dc.subjectBinary decision diagram-
dc.subjectDesign optimization-
dc.subjectGraph reduction-
dc.subjectSymbolic AC sensitivity-
dc.titleVariational analog integrated circuit design via symbolic sensitivity analysis-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ISCAS.2009.5118434-
dc.identifier.scopuseid_2-s2.0-70350148752-
dc.identifier.spage3002-
dc.identifier.epage3005-

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