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Conference Paper: Switchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET

TitleSwitchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET
Authors
Issue Date2020
PublisherIEEE.
Citation
2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 12-18 December 2020. In International Electron Devices Meeting (IEDM), 2020 How to Cite?
AbstractWe propose a novel triple-gated single transistor comprising monolayer MoS 2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS 2 n-FET and switchable easily through top-gate bias setting (V LOW / V HIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS 2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.
Persistent Identifierhttp://hdl.handle.net/10722/299186
ISSN

 

DC FieldValueLanguage
dc.contributor.authorChung, YY-
dc.contributor.authorCheng, CC-
dc.contributor.authorKang, BK-
dc.contributor.authorChueh, WC-
dc.contributor.authorWang, SY-
dc.contributor.authorChou, CH-
dc.contributor.authorHung, TYT-
dc.contributor.authorWang, SY-
dc.contributor.authorChang, WH-
dc.contributor.authorLi, LJ-
dc.contributor.authorChien, CH-
dc.date.accessioned2021-04-30T07:25:22Z-
dc.date.available2021-04-30T07:25:22Z-
dc.date.issued2020-
dc.identifier.citation2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 12-18 December 2020. In International Electron Devices Meeting (IEDM), 2020-
dc.identifier.issn0163-1918-
dc.identifier.urihttp://hdl.handle.net/10722/299186-
dc.description.abstractWe propose a novel triple-gated single transistor comprising monolayer MoS 2 channel to accomplish basic logic-gate functions. The NAND and NOR computing are compatible in the same MoS 2 n-FET and switchable easily through top-gate bias setting (V LOW / V HIGH = 0.75V / 2V). Moreover, separated top- and back-gate (TG and BG) operations in proposed device also enable the modulation of ON-state resistance by 7 orders of magnitude with maintaining low OFF-state current. The electrical response in devices with various back-gate designs could be explained in terms of energy band diagram through TCAD simulation. In this work, the multi-gated MoS 2 n-FETs have successfully demonstrated good logic-gate operation and large ON-OFF ratio modulation, which provide a new perspective in device design for future logic and even in-memory computing applications.-
dc.languageeng-
dc.publisherIEEE.-
dc.relation.ispartofInternational Electron Devices Meeting (IEDM)-
dc.titleSwitchable NAND and NOR Logic Computing in Single Triple-Gate Monolayer MoS2 n-FET-
dc.typeConference_Paper-
dc.identifier.emailLi, LJ: lanceli1@hku.hk-
dc.identifier.authorityLi, LJ=rp02799-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/IEDM13553.2020.9372072-
dc.identifier.scopuseid_2-s2.0-85102919144-
dc.identifier.hkuros700003941-

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