Sub-0.5 nm interfacial dielectric enables superior electrostatics: 65 mV/dec top-gated carbon nanotube FETs at 15 nm Gate Length

Abstract

To realize superior electrostatic control, a gate oxide bilayer for carbon nanotubes (CNT) is employed consisting of a 0.35 nm interfacial dielectric (k=7.8) and 2.5 nm high-k ALD dielectric (k=24). Using experimentally measured dielectric constants on sp2 carbon and minimum oxide thickness on CNT, a COX on CNT of 2.94×10-10 F/m is calculated for top-gate geometry. Gate leakage sub-1 pA/CNT is measured at 0.7V, better than the sub-5 nm node technology target. Top-gated carbon nanotube field effect transistors in this paper have 65 mV/dec subthreshold slope and DIBL as low as 20 mV/V at 15 nm gate length. Negligible hysteresis and no degradation in drive current from the top-gate process is observed. TCAD modeling predicts this approach will enable 68 mV/dec for top-gate CNFET with 10 nm LG, 1 nm CNT diameter and 250 CNT/μm, revealing a path to energy and performance gains from a CNT transistor technology.