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Conference Paper: High Performance WSe 2 Transistors with Multilayer Graphene Source/Drain

TitleHigh Performance WSe <inf>2</inf> Transistors with Multilayer Graphene Source/Drain
Authors
Lien, ChenhsinTang, Hao LingChiu, Ming HuiHou, Kuan JhihYang, Shih HsienSu, Jhih FongLin, Yen FuLi, Lain Jong
KeywordsGraphene
WSe 2
raised source/drain
Issue Date2018
Citation
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, 2018, article no. 8565030 How to Cite?
DOI: http://dx.doi.org/10.1109/ICSICT.2018.8565030
AbstractP-channel WSe FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the I /I ratio can be enhanced to 10 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact. 2 2 2 on off 8
Persistent Identifierhttp://hdl.handle.net/10722/298293

 

DC FieldValueLanguage
dc.contributor.authorLien, Chenhsin-
dc.contributor.authorTang, Hao Ling-
dc.contributor.authorChiu, Ming Hui-
dc.contributor.authorHou, Kuan Jhih-
dc.contributor.authorYang, Shih Hsien-
dc.contributor.authorSu, Jhih Fong-
dc.contributor.authorLin, Yen Fu-
dc.contributor.authorLi, Lain Jong-
dc.date.accessioned2021-04-08T03:08:05Z-
dc.date.available2021-04-08T03:08:05Z-
dc.date.issued2018-
dc.identifier.citation2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, 2018, article no. 8565030-
dc.identifier.urihttp://hdl.handle.net/10722/298293-
dc.description.abstractP-channel WSe FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the I /I ratio can be enhanced to 10 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact. 2 2 2 on off 8-
dc.languageeng-
dc.relation.ispartof2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings-
dc.subjectGraphene-
dc.subjectWSe 2-
dc.subjectraised source/drain-
dc.titleHigh Performance WSe <inf>2</inf> Transistors with Multilayer Graphene Source/Drain-
dc.typeConference_Paper-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ICSICT.2018.8565030-
dc.identifier.scopuseid_2-s2.0-85060285656-
dc.identifier.spagearticle no. 8565030-
dc.identifier.epagearticle no. 8565030-

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