New efficient hardware structures for adaptive filtering algorithms and their practical applications

Abstract

Efficient hardware implementation of advanced adaptive filtering (AF) algorithms is an important problem both in academia and industries. This thesis aims to develop novel hardware structures as well as design and analysis methods for two state-of-the-arts AF algorithms, namely the variable step-size (VSS) transform domain normalized least mean squares (TDNLMS) algorithm and the variable forgetting factor (VFF) recursive least squares algorithm (RLS), and investigate their applications to adaptive beamforming (ABF) and subspace tracking. Firstly, a new division-free variable regularized (VR) switch-mode noise constrained (SNC) TDNLMS algorithm for complex inputs and its efficient hardware realization for a generalized sidelobe canceller (GSC)-based ABF are proposed. Simulation results show that the use of VSS offers improved convergence speed as well as steady state MSE over conventional TDNLMS and LMS-based ABFs. Moreover, the VR scheme can effectively mitigate signal cancellation due to possible mismatches in steering vector. The proposed division-free ABF is implemented in field programmable gate array (FPGA) and it offers 27% higher throughput, nearly 22% reduction of DSP blocks used and 22% look-up tables over the conventional divider implementation for an 8-element ULA. Secondly, a new multiplier-less VR VFF RLS algorithm and its efficient hardware realization is proposed. It employs a discrete set of FFs so that their multiplications can be realized as canonical signed digits for efficient realization. Moreover, the cubic root and division operations involved in the locally optimal VFF RLS can be avoided. The same approach can also be used to realize the VR parameter. The proposed architecture is further extended to the projection approximation subspace tracking (PAST) algorithm resulting in an efficient realization of the VR-VFF-PAST algorithm. A modular multiple deflations (MD) approach is also proposed for providing more flexible tradeoffs between hardware resources and performance than the conventional PAST-d approach. Simulation results using the proposed VR-VFF-PAST algorithm offers faster convergence speed than conventional fixed FF method. A hardware architecture of the proposed algorithm based on the QR decomposition is proposed and is implemented on FPGA with a maximum operating speed of 143MHz. Compared with the lower complexity structure with deflation dimension of , the steady-state error for the more complex P=4 realization is decreased by 45%, which demonstrated the more flexible tradeoff of the proposed MD approach. Finally, the wordlength optimization problem of the VSS-TDNLMS adaptive filtering algorithm is studied. The problem is important as hardware simulation usually takes long time to complete and finding the right wordlength for the variables usually requires repeated trial and error. The proposed design methodology makes use of a theoretical model to predict the excess mean squares error (EMSE) of the adaptive filter under finite wordlength effect so as to speed up the search for optimal wordlength and hardware complexity to achieve a given EMSE performance. Moreover, a systematic approach for avoiding overflow and utilizing the hardware resources as parameterized by the wordlength of the intermediate variables used is proposed. An efficient pipelined hardware structure for implementing the VSS-TDNLMS in FPGA is developed to demonstrate the usefulness of the proposed methodology.