Fundamental Limit to Scaling Si Field-Effect Transistors Due to Source-to-Drain Direct Tunneling

Abstract

How far can the miniaturization of metal–oxide–semiconductor field-effect transistors (MOSFETs) continue is a recurring question, essential to all aspects of digital technology. Recent claims of well-performing MOSFETs with gate lengths below 4 nm apparently defy the fundamental limit of source-to-drain direct tunneling (SDDT). Here, we investigate that limit by simulating gate-all-around Si nanowire FETs with gate lengths between 8 and 3 nm using the state-of-the-art atomistic quantum transport modeling. We find that at 3-nm gate length, the current is dominated by SDDT, resulting in large source–drain leakage and poor switching performance even if the gate modulates the potential barrier between the source and drain sufficiently well. However, at 6-nm gate-length SDDT barely starts to degrade the subthreshold characteristics at large drain bias, and the ballistic ON-/OFF-current ratio is ∼10 6 with a subthreshold swing of 70 mV/decade, on par with contemporary Si technology. This means that in the best case, the technology roadmap could potentially be extended for several generations beyond the currently projected nodes. In addition, the results substantiate that the experimental devices with the claimed gate lengths below 6 nm in fact operate with a longer effective gate lengths. © 2019 IEEE.