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Article: Effects of Gate Electron Concentration on the Performance of Pentacene Organic Thin-Film Transistors
Title | Effects of Gate Electron Concentration on the Performance of Pentacene Organic Thin-Film Transistors |
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Authors | |
Keywords | Logic gates Dielectrics Pentacene Silicon Organic thin film transistors |
Issue Date | 2018 |
Publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 |
Citation | IEEE Electron Device Letters, 2018, v. 39 n. 7, p. 963-966 How to Cite? |
Abstract | Bottom-gated pentacene organic thin-film transistors (OTFTs) with NdTaON as high-k gate dielectric have been fabricated on substrates with different resistivities: 0.005 Ω · cm, 0.3~0.9 Ω · cm, and 1~5 Ω · cm for n-Si wafers, and 35 Ω/sq for ITO-coated glass. On the three n-Si substrates, the dielectric surface roughness and pentacene grain size are nearly the same, but the carrier mobility of the OTFTs show an obvious increase with decreasing resistivity, indicating that the gate electron concentration can affect the device performance. Despite the much larger dielectric surface roughness and smaller pentacene grain size, the OTFT on the ITO-coated glass shows the highest carrier mobility. These effects are attributed to remote phonon scattering on the channel carriers, which has been strongly screened by the electrons in the gate electrode. According to the measurement on the mobility degradation at high temperature, the remote phonon scattering is determined to be the dominant factor affecting the carrier mobility. As a result, the OTFT on ITO glass can achieve a high carrier mobility of 2.43 cm 2 /V · s and a small threshold voltage of -0.10 V. |
Persistent Identifier | http://hdl.handle.net/10722/278160 |
ISSN | 2023 Impact Factor: 4.1 2023 SCImago Journal Rankings: 1.250 |
ISI Accession Number ID |
DC Field | Value | Language |
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dc.contributor.author | MA, YX | - |
dc.contributor.author | HAN, CY | - |
dc.contributor.author | TANG, WM | - |
dc.contributor.author | Lai, PT | - |
dc.date.accessioned | 2019-10-04T08:08:38Z | - |
dc.date.available | 2019-10-04T08:08:38Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | IEEE Electron Device Letters, 2018, v. 39 n. 7, p. 963-966 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10722/278160 | - |
dc.description.abstract | Bottom-gated pentacene organic thin-film transistors (OTFTs) with NdTaON as high-k gate dielectric have been fabricated on substrates with different resistivities: 0.005 Ω · cm, 0.3~0.9 Ω · cm, and 1~5 Ω · cm for n-Si wafers, and 35 Ω/sq for ITO-coated glass. On the three n-Si substrates, the dielectric surface roughness and pentacene grain size are nearly the same, but the carrier mobility of the OTFTs show an obvious increase with decreasing resistivity, indicating that the gate electron concentration can affect the device performance. Despite the much larger dielectric surface roughness and smaller pentacene grain size, the OTFT on the ITO-coated glass shows the highest carrier mobility. These effects are attributed to remote phonon scattering on the channel carriers, which has been strongly screened by the electrons in the gate electrode. According to the measurement on the mobility degradation at high temperature, the remote phonon scattering is determined to be the dominant factor affecting the carrier mobility. As a result, the OTFT on ITO glass can achieve a high carrier mobility of 2.43 cm 2 /V · s and a small threshold voltage of -0.10 V. | - |
dc.language | eng | - |
dc.publisher | IEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 | - |
dc.relation.ispartof | IEEE Electron Device Letters | - |
dc.rights | IEEE Electron Device Letters. Copyright © IEEE. | - |
dc.rights | ©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | - |
dc.subject | Logic gates | - |
dc.subject | Dielectrics | - |
dc.subject | Pentacene | - |
dc.subject | Silicon | - |
dc.subject | Organic thin film transistors | - |
dc.title | Effects of Gate Electron Concentration on the Performance of Pentacene Organic Thin-Film Transistors | - |
dc.type | Article | - |
dc.identifier.email | Lai, PT: laip@eee.hku.hk | - |
dc.identifier.authority | Lai, PT=rp00130 | - |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/LED.2018.2832220 | - |
dc.identifier.scopus | eid_2-s2.0-85046365181 | - |
dc.identifier.hkuros | 306901 | - |
dc.identifier.volume | 39 | - |
dc.identifier.issue | 7 | - |
dc.identifier.spage | 963 | - |
dc.identifier.epage | 966 | - |
dc.identifier.isi | WOS:000437087400010 | - |
dc.publisher.place | United States | - |
dc.identifier.issnl | 0741-3106 | - |