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Article: High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing

TitleHigh-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing
Authors
Keywordsstreaming architecture
low-latency
high-throughput
FPGA
D-SWIM
Issue Date2019
PublisherMDPI AG. The Journal's web site is located at http://www.mdpi.com/journal/jimaging
Citation
Journal of Imaging, 2019, v. 5 n. 3, p. 34 How to Cite?
AbstractParallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to 56% of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of 329.5 MHz and reduction in power consumption by 45.7% comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM’s performance, where a pixel throughput of 4.5 Giga Pixel/s and 4.2 Giga Pixel/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to 30×.
Persistent Identifierhttp://hdl.handle.net/10722/275024
ISSN
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorSHI, R-
dc.contributor.authorWong, JS-
dc.contributor.authorSo, HKH-
dc.date.accessioned2019-09-10T02:33:53Z-
dc.date.available2019-09-10T02:33:53Z-
dc.date.issued2019-
dc.identifier.citationJournal of Imaging, 2019, v. 5 n. 3, p. 34-
dc.identifier.issn2313-433X-
dc.identifier.urihttp://hdl.handle.net/10722/275024-
dc.description.abstractParallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to 56% of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of 329.5 MHz and reduction in power consumption by 45.7% comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM’s performance, where a pixel throughput of 4.5 Giga Pixel/s and 4.2 Giga Pixel/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to 30×.-
dc.languageeng-
dc.publisherMDPI AG. The Journal's web site is located at http://www.mdpi.com/journal/jimaging-
dc.relation.ispartofJournal of Imaging-
dc.rightsThis work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.-
dc.subjectstreaming architecture-
dc.subjectlow-latency-
dc.subjecthigh-throughput-
dc.subjectFPGA-
dc.subjectD-SWIM-
dc.titleHigh-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing-
dc.typeArticle-
dc.identifier.emailWong, JS: jsjwong@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.3390/jimaging5030034-
dc.identifier.scopuseid_2-s2.0-85067639240-
dc.identifier.scopuseid_2-s2.0-85067639240-
dc.identifier.hkuros304139-
dc.identifier.volume5-
dc.identifier.issue3-
dc.identifier.spage34-
dc.identifier.epage34-
dc.identifier.isiWOS:000464312500001-
dc.publisher.placeSwitzerland-
dc.identifier.issnl2313-433X-

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