Graphical modelling of pinched hysteresis loops of memristors

Abstract

In this study, a graphical modelling approach of the pinched hysteresis loops exhibited by memristors is presented. This method provides a tool to emulate the hysteresis loop pinched at the origin, with the lobe area varying with the excitation frequency. The direction of the pinched hysteresis loop can be controlled. This graphical modelling method provides an alternative to describe the behaviour of memristors without deriving the coupled non-linear differential equations typically required for physical memristors. The method has been successfully applied to model the Hewlett–Packard memristor device.