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Conference Paper: Analysis of silicon dioxide interface transition region in MOS structures
| Title | Analysis of silicon dioxide interface transition region in MOS structures |
|---|---|
| Authors | |
| Issue Date | 2007 |
| Citation | 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, 2007, p. 149-152 How to Cite? |
| Abstract | We study the Si(100) inversion layer quantisation, capacitance and tunnelling characteristics in the case of a gradual band gap transition at the Si/SiO2 interface. A linear band gap transition of 0.5 nm at the SiO2 side results in nearly 20% redistribution of carriers from the 2-fold to the 4-fold degenerate valley, due to the greater wave-function penetration and sub-band level lowering for the 4-fold valley. The gate capacitance is enhanced by up to 12% for a 1.0 nm nominal oxide thickness, and the direct tunnelling current density increases by an order of magnitude. |
| Persistent Identifier | http://hdl.handle.net/10722/221313 |
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Markov, S. | - |
| dc.contributor.author | Barin, N. | - |
| dc.contributor.author | Fiegna, C. | - |
| dc.contributor.author | Roy, S. | - |
| dc.contributor.author | Sangiorgi, E. | - |
| dc.contributor.author | Asenov, A. | - |
| dc.date.accessioned | 2015-11-18T06:08:58Z | - |
| dc.date.available | 2015-11-18T06:08:58Z | - |
| dc.date.issued | 2007 | - |
| dc.identifier.citation | 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007, 2007, p. 149-152 | - |
| dc.identifier.uri | http://hdl.handle.net/10722/221313 | - |
| dc.description.abstract | We study the Si(100) inversion layer quantisation, capacitance and tunnelling characteristics in the case of a gradual band gap transition at the Si/SiO2 interface. A linear band gap transition of 0.5 nm at the SiO2 side results in nearly 20% redistribution of carriers from the 2-fold to the 4-fold degenerate valley, due to the greater wave-function penetration and sub-band level lowering for the 4-fold valley. The gate capacitance is enhanced by up to 12% for a 1.0 nm nominal oxide thickness, and the direct tunnelling current density increases by an order of magnitude. | - |
| dc.language | eng | - |
| dc.relation.ispartof | 2007 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2007 | - |
| dc.title | Analysis of silicon dioxide interface transition region in MOS structures | - |
| dc.type | Conference_Paper | - |
| dc.description.nature | link_to_subscribed_fulltext | - |
| dc.identifier.scopus | eid_2-s2.0-62449153881 | - |
| dc.identifier.spage | 149 | - |
| dc.identifier.epage | 152 | - |