Latency-aware dynamic voltage and frequency scaling on many-core architectures for data-intensive applications

Abstract

Low power is an important design requirement for HPC systems nowadays. Dynamic voltage and frequency scaling (DVFS) has become the commonly used and efficient technology to achieve a trade-off between power consumption and system performance. However, most of the prior work using DVFS did not take into account the latency of voltage/frequency scaling, which is a critical factor in real hardware determining the efficiency of the power management algorithm. This paper investigates the latency aspects of DVFS on a real many-core hardware platform. We propose a latency-aware DVFS algorithm to achieve profile-guided power management to avoid aggressive power state transitions. We evaluate our algorithm on the Intel SCC platform using a data-intensive benchmark, Graph 500. The experimental results not only show impressive potential for energy saving in data-intensive applications (up to 31% energy saving and 60% EDP reduction), but also evaluate the efficiency of our latency-aware DVFS algorithm which achieves 12.0% extra energy saving and 5.0% extra EDP reduction, while increasing the execution performance by 22.4%. © 2014 IEEE.