CLOCKING SCHEMES FOR HIGH-SPEED DIGITAL SYSTEMS.

Abstract

Based on a worst case analysis, clocking schemes for high-performance systems are analyzed. These are 1- and 2-phase systems using simple clocked latches, and 1-phase systems using edge-triggered D-flip-flops. Within these categories (any of which may be preferable in a given situation), it is shown how optimal tradeoffs can be made by appropriately choosing the parameters of the clocking system as a function of the technology parameters. The tradeoffs involve the clock period (which determines the data rate), and the tolerances that must be enforced on the propagation delays through the logic. Clock-pulse edge tolerances are shown to be an important factor. It is seen that, for systems using latches, their detrimental effects on the clock period can be converted to tighter bounds on the short-path delays by allowing D changes to lag behind the leading edges of the clock pulses and by using wider clock pulses or, in the case of 2-phase systems, by overlapping the clock pulses.