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Conference Paper: Design of VLSI switch for highly parallel multiprocessor system
Title | Design of VLSI switch for highly parallel multiprocessor system |
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Authors | |
Issue Date | 1990 |
Citation | Proceedings Of The Custom Integrated Circuits Conference, 1990 How to Cite? |
Abstract | The design of a large, multistage interconnection network that has been successfully constructed and used in a version of the RP3 system is described. The network hardware is scalable and can be used for systems consisting of anywhere from four to hundreds of processor and memory elements. An overview is given of the switch architecture, followed by the packaging structure. A description of the methodology used for logic design and verification of the large silicon chip is presented. |
Persistent Identifier | http://hdl.handle.net/10722/176096 |
ISSN | 2023 SCImago Journal Rankings: 1.122 |
DC Field | Value | Language |
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dc.contributor.author | Hsu, Yarsun | en_US |
dc.contributor.author | Benveniste, C | en_US |
dc.contributor.author | Ruedinger, J | en_US |
dc.contributor.author | Tan, CJ | en_US |
dc.date.accessioned | 2012-11-26T09:05:46Z | - |
dc.date.available | 2012-11-26T09:05:46Z | - |
dc.date.issued | 1990 | en_US |
dc.identifier.citation | Proceedings Of The Custom Integrated Circuits Conference, 1990 | en_US |
dc.identifier.issn | 0886-5930 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/176096 | - |
dc.description.abstract | The design of a large, multistage interconnection network that has been successfully constructed and used in a version of the RP3 system is described. The network hardware is scalable and can be used for systems consisting of anywhere from four to hundreds of processor and memory elements. An overview is given of the switch architecture, followed by the packaging structure. A description of the methodology used for logic design and verification of the large silicon chip is presented. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Proceedings of the Custom Integrated Circuits Conference | en_US |
dc.title | Design of VLSI switch for highly parallel multiprocessor system | en_US |
dc.type | Conference_Paper | en_US |
dc.identifier.email | Tan, CJ: ctan@eti.hku.hk | en_US |
dc.identifier.authority | Tan, CJ=rp01379 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.scopus | eid_2-s2.0-0025593922 | en_US |
dc.identifier.scopusauthorid | Hsu, Yarsun=13408051800 | en_US |
dc.identifier.scopusauthorid | Benveniste, C=6603204709 | en_US |
dc.identifier.scopusauthorid | Ruedinger, J=14066364600 | en_US |
dc.identifier.scopusauthorid | Tan, CJ=22981715400 | en_US |
dc.identifier.issnl | 0886-5930 | - |