Approach to behavioral synthesis for loop-based BIST

Abstract

This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of the BIST scheme during behavioral synthesis processes, an area optimal BIST solution can be obtained. This approach is based on the use of test resources reusability which results in a fewer number of registers being modified as BIST registers. This is achieved by incorporating testability constraints during register assignment operations. Experimental results on benchmarks are presented to demonstrate the effectiveness of the approach.