Auxiliary Data Compression and View Synthesis Technologies for 3D/Multiview Videos


Grant Data
Project Title
Auxiliary Data Compression and View Synthesis Technologies for 3D/Multiview Videos
Principal Investigator
Professor Chan, Shing Chow   (Project Coordinator (PC))
Co-Investigator(s)
Mr Lam Hoson   (Co-Investigator)
Duration
11
Start Date
2017-01-03
Completion Date
2017-12-31
Amount
206782
Conference Title
Auxiliary Data Compression and View Synthesis Technologies for 3D/Multiview Videos
Keywords
3D/Multiview Videos, Auxiliary Data Compression, View Synthesis Technologies
Discipline
Others - Electrical and Electronic Engineering
Panel
Engineering (E)
HKU Project Code
InP/347/16
Grant Type
Innovation and Technology Fund Internship Programme
Funding Year
2015
Status
Completed
Objectives
The present proposal is a joint effort of Marvel Digital Limited and the digital signal processing (DSP) research group at the University of Hong Kong. Marvel Digital Limited is a leading provider of multiview auto-stereoscopic displays (4K autostereoscopic displays) and related conversion technologies. The DSP group of the University of HK is a world-renowned research group in multiview capture, media processing and transmission technologies. The project aims to develop cutting edge compression and view synthesis technologies for a proposal to be submitted to the Research Institute of Ministry of Broadcasting for the consideration as a China Compression standard on 3D and multiview videos. Technologically, there are three main objectives in this project: 1) Development of the auxiliary data compression and view synthesis technologies for possible contribution to the China Compression standard on 3D/multiview videos. 2) Development of graphic processing units (GPUs)-accelerated version of the algorithms for demonstrating a real-time 3D video codec for autostereoscopic displays, which is intended for video phone or conferencing applications. 3) Development of hardware architecture of the decoder and key hardware modules on Field Programmable Gate Array (FPGA). These modules will form key Intellectual Properties (IPs) for developing low-cost integrated circuits (ICs) to support the decoder algorithms developed.