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Browsing by Author Jaiswal, MK
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Showing results 1 to 20 of 25
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Title
Author(s)
Issue Date
Views
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division
Journal:
Circuits, Systems, and Signal Processing
Jaiswal, MK
So, HKH
2018
53
Architecture for dual-mode quadruple precision floating point adder
Proceeding/Conference:
IEEE Computer Society Annual Symposium on VLSI
Jaiswal, MK
Bogaraju, SV
So, HKH
2015
42
Architecture for quadruple precision floating point division with multi-precision support
Proceeding/Conference:
International Conference on Application-Specific Systems, Architecture and Processors (ASAP) Proceedings
Jaiswal, MK
So, HKH
2016
58
Architecture Generator for Type-3 Unum Posit Adder/Subtractor
Proceeding/Conference:
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Jaiswal, MK
So, HKH
2018
82
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
Jaiswal, MK
So, HKH
2017
64
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
Journal:
Microelectronics Journal
Jaiswal, MK
Cheung, RCC
2013
76
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division
Proceeding/Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Jaiswal, MK
Cheung, RCC
Balakrishnan, M
Paul, K
2014
34
Configurable Architectures For Multi-mode Floating Point Adders
Journal:
IEEE Transactions On Circuits And Systems I: Regular Papers
Jaiswal, MK
Bogaraju, SV
So, HKH
Balakrishnan, M
Paul, K
Cheung, RCC
2015
36
Design of quadruple precision multiplier architectures with SIMD single and double precision support
Journal:
Integration: the VLSI journal
Jaiswal, MK
So, HKH
2019
17
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)
Proceeding/Conference:
International Conference on Field Programmable Logic and Applications
Ullah, Z
Jaiswal, MK
Cheung, RCC
2013
41
DSP48E efficient floating point multiplier architectures on FPGA
Proceeding/Conference:
International Conference on VLSI Design & International Conference on Embedded Systems (VLSID)
Jaiswal, MK
So, HKH
2017
56
Dual-Mode Double Precision / Two-Parallel Single Precision Floating Point Multiplier Architecture
Proceeding/Conference:
IFIP International Conference on Very Large Scale Integration (VLSI-SoC)
Jaiswal, MK
So, HKH
2015
40
Dual-mode double precision division architecture
Proceeding/Conference:
International Midwest Symposium on Circuits and Systems Conference Proceedings
Jaiswal, MK
So, HKH
2016
36
E-TCAM: An Efficient SRAM-Based Architecture for TCAM
Journal:
Circuits, Systems, and Signal Processing
Ullah, Z
Jaiswal, MK
Cheung, RCC
2014
55
Fast Content Updating Algorithm For An Sram-based Tcam On Fpga
Journal:
IEEE Embedded Systems Letters
Farkhanda, S
Ullah, Z
Jaiswal, MK
2018
26
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform
Proceeding/Conference:
IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig)
Ng, HC
Wang, M
Chung, BMF
Bogaraju, SV
Jaiswal, MK
Ho, SMH
Tsia, KKM
Shum, HC
So, HKH
2016
51
PACoGen: A Hardware Posit Arithmetic Core Generator
Journal:
IEEE Access
Jaiswal, MK
So, HKH
2019
17
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA
Proceeding/Conference:
IEEE International Conference on FieId-Programmable Technology Proceedings
Wang, M
Ng, HC
Chung, BMF
Bogaraju, SV
Jaiswal, MK
Tsia, KKM
Shum, HC
So, HKH
2016
12
Series Expansion based Efficient Architectures for Double Precision Floating Point Division
Journal:
Circuits, Systems, and Signal Processing
Jaiswal, MK
Cheung, RCC
Balakrishnan, M
Paul, K
2014
38
Taylor series based architecture for Quadruple Precision Floating Point Division
Proceeding/Conference:
IEEE Computer Society Annual Symposium on VLSI
Jaiswal, MK
So, HKH
2016
57
