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Conference Paper: Performance evaluation of FPGA implementations of high-speed addition algorithms

TitlePerformance evaluation of FPGA implementations of high-speed addition algorithms
Authors
KeywordsFPGA
Addition
Performance evaluation
Carry-ripple adder
Carry-completion adder
Issue Date1996
PublisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://www.spie.org/app/Publications/index.cfm?fuseaction=proceedings
Citation
High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, Boston, Massachusetts, USA, 20-21 November 1996, v. 2914, p. 26-33 How to Cite?
AbstractDriven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.
Persistent Identifierhttp://hdl.handle.net/10722/46578
ISSN

 

DC FieldValueLanguage
dc.contributor.authorYu, WWHen_HK
dc.contributor.authorXing, Sen_HK
dc.date.accessioned2007-10-30T06:53:19Z-
dc.date.available2007-10-30T06:53:19Z-
dc.date.issued1996en_HK
dc.identifier.citationHigh-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, Boston, Massachusetts, USA, 20-21 November 1996, v. 2914, p. 26-33en_HK
dc.identifier.issn0277-786Xen_HK
dc.identifier.urihttp://hdl.handle.net/10722/46578-
dc.description.abstractDriven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.en_HK
dc.format.extent371620 bytes-
dc.format.extent3380 bytes-
dc.format.mimetypeapplication/pdf-
dc.format.mimetypetext/plain-
dc.languageengen_HK
dc.publisherS P I E - International Society for Optical Engineering. The Journal's web site is located at http://www.spie.org/app/Publications/index.cfm?fuseaction=proceedingsen_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsS P I E - the International Society for Optical Proceedings. Copyright © S P I E - International Society for Optical Engineering.en_HK
dc.rightsCopyright xxxx (year) Society of Photo-Optical Instrumentation Engineers. This paper was published in High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, Boston, Massachusetts, USA, 20-21 November 1996, v. 2914, p. 26-33 and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.en_HK
dc.subjectFPGAen_HK
dc.subjectAdditionen_HK
dc.subjectPerformance evaluationen_HK
dc.subjectCarry-ripple adderen_HK
dc.subjectCarry-completion adderen_HK
dc.titlePerformance evaluation of FPGA implementations of high-speed addition algorithmsen_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0277-786X&volume=2914&spage=26&epage=33&date=1996&atitle=Performance+evaluation+of+FPGA+implementations+of+high-speed+addition+algorithmsen_HK
dc.description.naturepublished_or_final_versionen_HK
dc.identifier.doi10.1117/12.255826en_HK
dc.identifier.hkuros28911-

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