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Conference Paper: On the sub-nm EOT scaling of high-κ gate stacks

TitleOn the sub-nm EOT scaling of high-κ gate stacks
Authors
Issue Date2008
Citation
ULIS 2008 - 9th International Conference on ULtimate Integration of Silicon, 2008, p. 99-102 How to Cite?
AbstractIncorporating recent data for the Si/SiO2 and SiO 2/HfO2 interface properties, we simulate the impact of bandgap and permittivity transitions on high-κ (HK) gate-stack (GS) metal-oxide-semiconductor (MOS) devices, scaled according to the requirements for effective oxide thickness (EOT) reduction in bulk MOSFETs. Si/SiO 2 transition effects dominate, lowering the EOT, increasing over 10 times gate leakage, and shifting over 20% of electrons from the 2-fold, to the 4-fold degenerate valley. Accounting for the interface transition effects is important for accurate HKGS device characterisation and predictive modelling. © 2008 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/221311

 

DC FieldValueLanguage
dc.contributor.authorMarkov, S.-
dc.contributor.authorRoy, S.-
dc.contributor.authorFiegna, C.-
dc.contributor.authorSangiorgi, E.-
dc.contributor.authorAsenov, A.-
dc.date.accessioned2015-11-18T06:08:58Z-
dc.date.available2015-11-18T06:08:58Z-
dc.date.issued2008-
dc.identifier.citationULIS 2008 - 9th International Conference on ULtimate Integration of Silicon, 2008, p. 99-102-
dc.identifier.urihttp://hdl.handle.net/10722/221311-
dc.description.abstractIncorporating recent data for the Si/SiO2 and SiO 2/HfO2 interface properties, we simulate the impact of bandgap and permittivity transitions on high-κ (HK) gate-stack (GS) metal-oxide-semiconductor (MOS) devices, scaled according to the requirements for effective oxide thickness (EOT) reduction in bulk MOSFETs. Si/SiO 2 transition effects dominate, lowering the EOT, increasing over 10 times gate leakage, and shifting over 20% of electrons from the 2-fold, to the 4-fold degenerate valley. Accounting for the interface transition effects is important for accurate HKGS device characterisation and predictive modelling. © 2008 IEEE.-
dc.languageeng-
dc.relation.ispartofULIS 2008 - 9th International Conference on ULtimate Integration of Silicon-
dc.titleOn the sub-nm EOT scaling of high-κ gate stacks-
dc.typeConference_Paper-
dc.description.natureLink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ULIS.2008.4527149-
dc.identifier.scopuseid_2-s2.0-49049093664-
dc.identifier.spage99-
dc.identifier.epage102-

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