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Conference Paper: Fabrication and electrical characterization of MONOS memory with novel high-κ gate stack

TitleFabrication and electrical characterization of MONOS memory with novel high-κ gate stack
Authors
KeywordsBlocking layer
Charge storage layer
High-κ gate stack
MONOS memory
Tunneling layer
Issue Date2009
PublisherIEEE.
Citation
The IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-524 How to Cite?
AbstractA novel high-κ gate stack structure with HfON/SiO 2 as dual tunneling layer (DTL), AIN as charge storage layer (CSL) and HfAIO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si 3N 4/SiO 2 as DTL, HfO 2 as CSL and Al 2O 3 as BL. Results show a large memory window of 3.55 V at PIE voltage of +8 V/-I5 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAIO/AIN/(HfON/SiO 2)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-κ HfON/SiO 2 DTL, high trapping efficiency of the high-κ AIN material and effective blocking role of the high-κ HfAIO BL. ©2009 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/126173
ISBN
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorLiu, Len_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorChan, CLen_HK
dc.contributor.authorLai, PTen_HK
dc.date.accessioned2010-10-31T12:13:45Z-
dc.date.available2010-10-31T12:13:45Z-
dc.date.issued2009en_HK
dc.identifier.citationThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-524en_HK
dc.identifier.isbn978-1-4244-4297-3-
dc.identifier.urihttp://hdl.handle.net/10722/126173-
dc.description.abstractA novel high-κ gate stack structure with HfON/SiO 2 as dual tunneling layer (DTL), AIN as charge storage layer (CSL) and HfAIO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with Si 3N 4/SiO 2 as DTL, HfO 2 as CSL and Al 2O 3 as BL. Results show a large memory window of 3.55 V at PIE voltage of +8 V/-I5 V, high program/erase speed and good retention characteristic can be achieved using the novel Au/ HfAIO/AIN/(HfON/SiO 2)/Si gate stack structure. The main mechanisms lie in the enhanced electron injection through the high-κ HfON/SiO 2 DTL, high trapping efficiency of the high-κ AIN material and effective blocking role of the high-κ HfAIO BL. ©2009 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE.-
dc.relation.ispartof2009 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2009en_HK
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsIEEE International Conference on Electron Devices and Solid-State Circuits. Copyright © IEEE.-
dc.rights©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectBlocking layeren_HK
dc.subjectCharge storage layeren_HK
dc.subjectHigh-κ gate stacken_HK
dc.subjectMONOS memoryen_HK
dc.subjectTunneling layeren_HK
dc.titleFabrication and electrical characterization of MONOS memory with novel high-κ gate stacken_HK
dc.typeConference_Paperen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=978-1-4244-4297-3&volume=&spage=521&epage=524&date=2009&atitle=Fabrication+and+electrical+characterization+of+MONOS+memory+with+novel+high-κ+gate+stack-
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/EDSSC.2009.5394199en_HK
dc.identifier.scopuseid_2-s2.0-77949589336en_HK
dc.identifier.hkuros180696en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77949589336&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage521en_HK
dc.identifier.epage524en_HK
dc.identifier.isiWOS:000289818000133-
dc.description.otherThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2009, Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 521-524-
dc.identifier.scopusauthoridLiu, L=35778603700en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridChan, CL=8507083700en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK

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