|
fpga |
7 |
|
electrical engineering education |
6 |
|
introductory engineering |
6 |
|
microfluidics |
6 |
|
project-based learning |
6 |
|
quantitative phase imaging |
6 |
|
rube goldberg machine |
6 |
|
single-cell imaging |
6 |
|
single‐cell imaging |
6 |
|
ultrafast imaging |
6 |
|
imaging flow cytometry |
5 |
|
label-free biophysical phenotyping |
5 |
|
ultrafast single cell imaging |
5 |
|
bright field imaging |
4 |
|
cell classification |
4 |
|
convolutional neural network |
4 |
|
deep learning |
4 |
|
multiclass classification |
4 |
|
4-dimensional convolution |
3 |
|
adaptive beamformer |
3 |
|
adc |
3 |
|
application examples |
3 |
|
bayesian model |
3 |
|
cell image classification |
3 |
|
clock frequencies |
3 |
|
clss |
3 |
|
computational efficiency |
3 |
|
computer hardware description languages |
3 |
|
convolutional neural network (cnn) |
3 |
|
convolutional neural networks |
3 |
|
cryptography |
3 |
|
field programmable gate arrays (fpga) |
3 |
|
field-programmable gate array (fpga) |
3 |
|
frequency multiplying circuits |
3 |
|
hardware architecture |
3 |
|
hyperspectral image (hsi) |
3 |
|
identity-based encryption (ibe) |
3 |
|
iir-filters |
3 |
|
image reconstruction |
3 |
|
land covers |
3 |
|
light field imaging |
3 |
|
light field super-resolution |
3 |
|
line scan super resolution |
3 |
|
low-latency inference |
3 |
|
multiplier circuits |
3 |
|
network encryptor |
3 |
|
nonparametric bayesian |
3 |
|
optical microscopy |
3 |
|
phase locked loops |
3 |
|
phase shift |
3 |
|
power engineering computing |
3 |
|
power system security |
3 |
|
quadrature phase shift keying |
3 |
|
remote sensing |
3 |
|
sigma-delta modulation |
3 |
|
signal processing |
3 |
|
smart power grids |
3 |
|
supersingular curve |
3 |
|
tate pairing |
3 |
|
adaptive beamforming |
2 |
|
algorithm architecture co-design |
2 |
|
approximation |
2 |
|
architecture designs |
2 |
|
array processing |
2 |
|
block sizes |
2 |
|
computational architecture |
2 |
|
computational imaging |
2 |
|
computational resources |
2 |
|
data representations |
2 |
|
dense matrices |
2 |
|
design considerations |
2 |
|
design space exploration |
2 |
|
development time |
2 |
|
digit recognition |
2 |
|
digital holographic reconstruction |
2 |
|
digital holography |
2 |
|
division-free |
2 |
|
dpacs |
2 |
|
dynamic pruning |
2 |
|
encoder-decoder |
2 |
|
experiential learning |
2 |
|
explorations |
2 |
|
field-programmable gate array |
2 |
|
gpu |
2 |
|
graphics processing units |
2 |
|
hardware acceleration |
2 |
|
hybrid cpu-gpu |
2 |
|
interdisciplinary |
2 |
|
internet of things |
2 |
|
medical ultrasound |
2 |
|
medical ultrasound imaging |
2 |
|
medical ultrasound systems |
2 |
|
motion compensation |
2 |
|
neural networks |
2 |
|
parallel processing |
2 |
|
performance |
2 |
|
power |
2 |
|
real-time realization |
2 |
|
sa imaging |
2 |
|
sar image |
2 |
|
shrinkage |
2 |
|
sparse |
2 |
|
sparse matrix-matrix multiplication |
2 |
|
speckle |
2 |
|
speckle filters |
2 |
|
superresolution |
2 |
|
synthetic aperture |
2 |
|
urban farming |
2 |
|
variable regularization |
2 |
|
variable step-size |
2 |
|
25 years |
1 |
|
acceleration |
1 |
|
adder |
1 |
|
agriculture |
1 |
|
analytic models |
1 |
|
architecture search |
1 |
|
arithmetic |
1 |
|
asic |
1 |
|
borph |
1 |
|
coarse-grained reconfigurable arrays |
1 |
|
commercial-off-the-shelf |
1 |
|
computer architecture |
1 |
|
configurable architecture |
1 |
|
d-swim |
1 |
|
design |
1 |
|
design productivity |
1 |
|
digital arithmetic |
1 |
|
division |
1 |
|
dual-mode architecture |
1 |
|
dual-mode arithmetic |
1 |
|
dual-mode division |
1 |
|
dynamic power |
1 |
|
dynamic power consumption |
1 |
|
dynamic power reduction |
1 |
|
embedded processors |
1 |
|
embedded systems |
1 |
|
field programmable gate arrays |
1 |
|
field-programmable gate arrays |
1 |
|
field-programmable logic and applications |
1 |
|
floating point addition |
1 |
|
floating point arithmetic |
1 |
|
floating point division |
1 |
|
fpga architectures |
1 |
|
fpga implementations |
1 |
|
fpgas |
1 |
|
fpl |
1 |
|
fsm |
1 |
|
future technologies |
1 |
|
graph processing |
1 |
|
gravf-m |
1 |
|
hardware design |
1 |
|
hardware engineering |
1 |
|
hardware process |
1 |
|
high level applications |
1 |
|
high-level synthesis |
1 |
|
high-throughput |
1 |
|
i/o bandwidth |
1 |
|
iterative architecture |
1 |
|
karatsuba multiplication |
1 |
|
learning (artificial intelligence) |
1 |
|
low-latency |
1 |
|
machine learning |
1 |
|
matrix |
1 |
|
matrix multiplication |
1 |
|
model |
1 |
|
modified booth multiplier |
1 |
|
multi-fpga architecture |
1 |
|
multi-mode arithmetic |
1 |
|
multi-mode multi-precision arithmetic |
1 |
|
multi-precision |
1 |
|
multi-precision arithmetic |
1 |
|
multi-precision division |
1 |
|
multiplier |
1 |
|
network compression |
1 |
|
neural nets |
1 |
|
neural network pruning |
1 |
|
operation scheduling |
1 |
|
peak performance |
1 |
|
performance modelling |
1 |
|
performance problems |
1 |
|
posit |
1 |
|
posit arithmetic |
1 |
|
precomputation |
1 |
|
quadruple precision arithmetic |
1 |
|
random access memory |
1 |
|
reconfigurable computer |
1 |
|
reconfigurable computers |
1 |
|
rnn |
1 |
|
robots |
1 |
|
shared memories |
1 |
|
significant papers |
1 |
|
simd |
1 |
|
simulation |
1 |
|
software process |
1 |
|
software program |
1 |
|
sparks |
1 |
|
sparse learning |
1 |
|
streaming architecture |
1 |
|
structured pruning |
1 |
|
sub-tractor |
1 |
|
subtractor |
1 |
|
support vector machines |
1 |
|
system-on-chip |
1 |
|
taylor series expansion division |
1 |
|
training |
1 |
|
universal number system |
1 |
|
unum |
1 |
|
verification |
1 |
|
vertex centric |
1 |
|
virtual memory |
1 |
|
workload balancing |
1 |
